High-performance montgomery modular multiplier with NTT and negative wrapped convolution

被引:0
|
作者
Ke, Hongfei [1 ]
Li, Hao [1 ]
Zhang, Peiyong [1 ]
机构
[1] Zhejiang Univ, Sch Micronano Elect, Hangzhou 310058, Peoples R China
基金
国家重点研发计划;
关键词
Number theoretic transform; Negative wrapped convolution; Montgomery modular multiplication; Parallel computation; TRANSFORMS;
D O I
10.1016/j.mejo.2023.106085
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Modular multiplication plays a crucial role in modern cryptography. Montgomery modular multiplication(MMM), one of the most classic and practical modular multiplication algorithms, has been widely used in cryptographic algorithms such as RSA, Diffie-Hellman algorithm, and Elliptic Curve Cryptography. In this paper, we incorporate negative wrapped convolution (NWC) into the FFT-based Montgomery modular multiplication to avoid the issue of zero-padding and use carry-save arithmetics for parallel computation. By utilizing coefficient pairs (pos_part and neg_part), we reconstruct the final result and eliminate the restrictions imposed by nega-cyclic parts. Moreover, Karatsuba-like algorithm is introduced for building fine-grained large integer multipliers. We have modified the parameter specifications for our design to meet requirements from diverse application scenarios. We implement the design on Xilinx Virtex-7 FPGA under different conditions and compare the results with the state-of-the-art MMM designs. The comparisons confirm that our design has the following characteristics: low latency for process, competitive area-latency-product(ALP), efficient DSP usage, and constant delay, which enhances security against timing attacks.
引用
收藏
页数:11
相关论文
共 50 条
  • [1] HIGH PERFORMANCE MONTGOMERY MODULAR MULTIPLIER WITH A NEW RECODING METHOD
    Manochehri, Kooroush
    Sadeghiyan, Babak
    Pourmozafari, Saadat
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2011, 20 (03) : 531 - 548
  • [2] High-performance Systolic Array Montgomery Multiplier for SIKE
    Ni, Ziying
    Kundi, Dur-E-Shahwar
    O'Neill, Maire
    Liu, Weiqiang
    2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2021,
  • [3] A Low-Cost High-Performance Montgomery Modular Multiplier Based on Pipeline Interleaving for IoT Devices
    Li, Hongshuo
    Ren, Shiwei
    Wang, Weijiang
    Zhang, Jingqi
    Wang, Xiaohua
    ELECTRONICS, 2023, 12 (15)
  • [4] A scalable architecture of high-performance Montgomery multiplier for design reuse
    Chen, HH
    Sun, YH
    Bai, GQ
    2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 1251 - 1255
  • [5] High Radix Montgomery Modular Multiplier on Modern FPGA
    Wang, Pingjian
    Liu, Zongbin
    Wang, Lei
    Gao, Neng
    2013 12TH IEEE INTERNATIONAL CONFERENCE ON TRUST, SECURITY AND PRIVACY IN COMPUTING AND COMMUNICATIONS (TRUSTCOM 2013), 2013, : 1484 - 1489
  • [6] Low latency high throughput Montgomery modular multiplier for RSA cryptosystem
    Parihar, Aashish
    Nakhate, Sangeeta
    ENGINEERING SCIENCE AND TECHNOLOGY-AN INTERNATIONAL JOURNAL-JESTECH, 2022, 30
  • [7] Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
    Kuang, Shiann-Rong
    Wu, Kun-Yi
    Lu, Ren-Yao
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (02) : 434 - 443
  • [8] Design of a High-Performance Iterative Barrett Modular Multiplier for Crypto Systems
    Zhang, Bo
    Cheng, Zeming
    Pedram, Massoud
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2024, 32 (05) : 897 - 910
  • [9] Manipulated Lookup Table Method for Efficient High-Performance Modular Multiplier
    Opasatian, Anawin
    Ikeda, Makoto
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2025, 33 (01) : 114 - 127
  • [10] A High-Performance Low-Power Barrett Modular Multiplier for Cryptosystems
    Zhang, Bo
    Cheng, Zeming
    Pedram, Massoud
    2021 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), 2021,