Hybrid quantum error correction in qubit architectures

被引:1
|
作者
Kristensen, Lasse Bjorn [1 ]
Kjaergaard, Morten [2 ,5 ]
Andersen, Christian Kraglund [3 ,6 ]
Zinner, Nikolaj Thomas [1 ,4 ]
机构
[1] Aarhus Univ, Dept Phys & Astron, DK-8000 Aarhus, Denmark
[2] MIT, Res Lab Elect, Cambridge, MA 02139 USA
[3] Swiss Fed Inst Technol, Dept Phys, CH-8093 Zurich, Switzerland
[4] Aarhus Univ, Aarhus Inst Adv Study, DK-8000 Aarhus, Denmark
[5] Univ Copenhagen, Niels Bohr Inst, Ctr Quantum Devices, DK-2100 Copenhagen, Denmark
[6] Delft Univ Technol, QuTech & Kavli Inst Nanosci, NL-2628 CJ Delft, Netherlands
基金
美国国家科学基金会;
关键词
SUPERCONDUCTING QUBITS; STATE; REALIZATION;
D O I
10.1103/PhysRevA.108.022403
中图分类号
O43 [光学];
学科分类号
070207 ; 0803 ;
摘要
Noise and errors are inevitable parts of any practical implementation of a quantum computer. As a result, large-scale quantum computation will require ways to detect and correct errors in quantum information. Here we present such a quantum error-correcting scheme for correcting the dominant phase and decay errors in superconducting qubit architectures using a hybrid approach combining autonomous correction based on engineered dissipation with traditional measurement-based quantum error correction. Using numerical simulations with realistic device parameters for superconducting circuits, we show that this scheme can achieve a five- to tenfold increase in storage time while using only six qubits for the encoding and two ancillary qubits for the operation of the autonomous correction, providing a potentially large reduction of qubit overhead compared to typical measurement-based error-correction schemes. Furthermore, the scheme relies on standard interactions and qubit driving available in most major quantum computing platforms, making it implementable in a wide range of architectures.
引用
收藏
页数:33
相关论文
共 50 条
  • [31] Compressor based hybrid approximate multiplier architectures with efficient error correction logic
    Uppugunduru, Anil Kumar
    Bharadwaj, S. Vignesh
    Ahmed, Syed Ershad
    COMPUTERS & ELECTRICAL ENGINEERING, 2022, 104
  • [32] A small error-correction code for protecting three-qubit quantum information
    Yang, CP
    Chu, SI
    Han, SY
    JETP LETTERS, 2004, 79 (05) : 236 - 240
  • [33] Quantum error correction and universal gate set operation on a binomial bosonic logical qubit
    Hu, L.
    Ma, Y.
    Cai, W.
    Mu, X.
    Xu, Y.
    Wang, W.
    Wu, Y.
    Wang, H.
    Song, Y. P.
    Zou, C. -L.
    Girvin, S. M.
    Duan, L-M.
    Sun, L.
    NATURE PHYSICS, 2019, 15 (05) : 503 - +
  • [34] Image Transmission Over Quantum Communication Systems With Three-Qubit Error Correction
    Jayasinghe, Udara
    Samarathunga, Prabhath
    Fernando, Thanuj
    Ganearachchi, Yasith
    Fernando, Anil
    ELECTRONICS LETTERS, 2025, 61 (01)
  • [35] Quantum error correction and universal gate set operation on a binomial bosonic logical qubit
    L. Hu
    Y. Ma
    W. Cai
    X. Mu
    Y. Xu
    W. Wang
    Y. Wu
    H. Wang
    Y. P. Song
    C.-L. Zou
    S. M. Girvin
    L-M. Duan
    L. Sun
    Nature Physics, 2019, 15 : 503 - 508
  • [36] Repeated quantum error correction on a continuously encoded qubit by real-time feedback
    Cramer, J.
    Kalb, N.
    Rol, M. A.
    Hensen, B.
    Blok, M. S.
    Markham, M.
    Twitchen, D. J.
    Hanson, R.
    Taminiau, T. H.
    NATURE COMMUNICATIONS, 2016, 7
  • [37] A small error-correction code for protecting three-qubit quantum information
    Chui-Ping Yang
    Shih-I Chu
    Siyuan Han
    Journal of Experimental and Theoretical Physics Letters, 2004, 79 : 236 - 240
  • [38] Analysis of physical requirements for simple three-qubit and nine-qubit quantum error correction on quantum-dot and superconductor qubits
    Sohn, IlKwon
    Tarucha, Seigo
    Choi, Byung-Soo
    PHYSICAL REVIEW A, 2017, 95 (01)
  • [39] Higher rank matricial ranges and hybrid quantum error correction
    Cao, Ningping
    Kribs, David W.
    Li, Chi-Kwong
    Nelson, Mike, I
    Poon, Yiu-Tung
    Zeng, Bei
    LINEAR & MULTILINEAR ALGEBRA, 2021, 69 (05): : 827 - 839
  • [40] CONCURRENT ERROR CORRECTION IN SYSTOLIC ARCHITECTURES
    COSENTINO, RJ
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1988, 7 (01) : 117 - 125