A Low Memory Requirement MobileNets Accelerator Based on FPGA for Auxiliary Medical Tasks

被引:3
|
作者
Lin, Yanru [1 ]
Zhang, Yanjun [2 ]
Yang, Xu [3 ]
机构
[1] Beijing Inst Technol, Sch Integrated Circuits & Elect, 5 South St, Beijing 100081, Peoples R China
[2] Beijing Inst Technol, Sch Cyberspace Sci & Technol, 5 South St, Beijing 100081, Peoples R China
[3] Beijing Inst Technol, Sch Comp Sci & Technol, 5 South St, Beijing 100081, Peoples R China
来源
BIOENGINEERING-BASEL | 2023年 / 10卷 / 01期
关键词
convolutional neural network; FPGA; hardware accelerator; MobileNetV2; auxiliary medical tasks;
D O I
10.3390/bioengineering10010028
中图分类号
Q81 [生物工程学(生物技术)]; Q93 [微生物学];
学科分类号
071005 ; 0836 ; 090102 ; 100705 ;
摘要
Convolutional neural networks (CNNs) have been widely applied in the fields of medical tasks because they can achieve high accuracy in many fields using a large number of parameters and operations. However, many applications designed for auxiliary checks or help need to be deployed into portable devices, where the huge number of operations and parameters of a standard CNN can become an obstruction. MobileNet adopts a depthwise separable convolution to replace the standard convolution, which can greatly reduce the number of operations and parameters while maintaining a relatively high accuracy. Such highly structured models are very suitable for FPGA implementation in order to further reduce resource requirements and improve efficiency. Many other implementations focus on performance more than on resource requirements because MobileNets has already reduced both parameters and operations and obtained significant results. However, because many small devices only have limited resources they cannot run MobileNet-like efficient networks in a normal way, and there are still many auxiliary medical applications that require a high-performance network running in real-time to meet the requirements. Hence, we need to figure out a specific accelerator structure to further reduce the memory and other resource requirements while running MobileNet-like efficient networks. In this paper, a MobileNet accelerator is proposed to minimize the on-chip memory capacity and the amount of data that is transferred between on-chip and off-chip memory. We propose two configurable computing modules: Pointwise Convolution Accelerator and Depthwise Convolution Accelerator, to parallelize the network and reduce the memory requirement with a specific dataflow model. At the same time, a new cache usage method is also proposed to further reduce the use of the on-chip memory. We implemented the accelerator on Xilinx XC7Z020, deployed MobileNetV2 on it, and achieved 70.94 FPS with 524.25 KB on-chip memory usage under 150 MHz.
引用
收藏
页数:15
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