A 12-bit 2.32 GS/s pipelined/SAR hybrid ADC with a high-linearity input buffer

被引：3

作者：

Guo, Xuehao ^{[1
]}

Li, Zhiyang ^{[1
]}

Fang, Hao ^{[1
]}

Jia, Zelin ^{[1
]}

Tian, Fuli ^{[1
]}

Song, Chunyi ^{[1
]}

Xu, Zhiwei ^{[1
]}

机构：

[1] Zhejiang Univ, Inst Marine Elect Engn, Ocean Coll, Hangzhou, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2023年 / 20卷 / 23期

关键词：

ADC; high-linearity input buffer; pipelined-SAR; timeinterleaved; INTERLEAVED SAR ADC; CMOS;

D O I：

10.1587/elex.20.20230369

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a 12-bit 2.32 GS/s time-interleaved pipelined/successive-approximation register (SAR) hybrid analog-to digital converter (ADC) implemented in 28 nm CMOS. To achieve high linearity at several GS/s, a pseudo-differential push-pull input buffer with floating-body technique is proposed. A pipelined/SAR hybrid architecture with dual-channel sampling multiplying digital-to-analog converter (MDAC) and one shared flash sub-ADC is used exploiting a simple calibration. The ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 55.68dB and a spurious-free-dynamic-range (SFDR) of 72.18dB at 1125MHz input and consumes 175 mW.

引用

页数：5

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