Comparing FPGA-Based Adders and Application to the Implementation of a Digital FIR Filter

被引：0

作者：

Woelfle, Justin ^{[1
]}

Chabini, Noureddine ^{[2
]}

Beguenane, Rachid ^{[2
]}

机构：

[1] Queens Univ, Dept Elect & Comp Engn, Kingston, ON, Canada

[2] Royal Mil Coll Canada, Dept Elect & Comp Engn, Kingston, ON, Canada

来源：

2023 IEEE CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, CCECE | 2023年

关键词：

FPGA; adder; multiplier; FIR filter;

D O I：

10.1109/CCECE58730.2023.10288654

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

Field Programmable Gate Arrays (FPGAs) are being used in the realization of real-life applications. Adders are required in data processing units and in the realization of other arithmetic operators. We compare three types of FPGA-based adders, propose optimizations, and use the non-optimized and optimized adders for realizing a digital Finite Impulse Response (FIR) filter on FPGA and we compare the implementations. As an FPGA platform, we used the Altera Cyclone IV. The used synthesis tool is the Quartus Prime 19.1 from Altera. Experimental results are provided and discussed.

引用

页数：4

共 50 条

[41] A networked FPGA-based hardware implementation of a neural network application
Restrepo, HF
Hoffmann, R
Perez-Uribe, A
Teuscher, C
Sanchez, E
2000 IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS, 2000, : 337 - 338
[42] Design of Full Digital Signal Generator and FIR Digital Filter System Based on FPGA
Zhang, Qianqian
Qu, Panrang
Sun, Shaohua
Yu, Erjun
Yan, Wen
2022 41ST CHINESE CONTROL CONFERENCE (CCC), 2022, : 4501 - 4506
[43] FPGA-based implementation of floating point processing element for the design of efficient FIR filters
John, Tintu Mary
Chacko, Shanty
IET COMPUTERS AND DIGITAL TECHNIQUES, 2021, 15 (04): : 296 - 301
[44] A FPGA-based implementation of data acquisition and processing for digital protective relays
Feng, T
Zhang, GQ
Wang, JH
Geng, YS
Zhang, H
2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, 2001, : 518 - +
[45] Systolic FIR Filter Design with Various Parallel Prefix Adders in FPGA: Performance Analysis
Uma, R.
Ponnian, Jebashini
2012 INTERNATIONAL SYMPOSIUM ON ELECTRONIC SYSTEM DESIGN (ISED 2012), 2012, : 111 - 115
[46] The Implementation methods of High Speed FIR Filter on FPGA
Li, Ying
Peng, Chungan
Yu, Dunshan
Zhang, Xing
2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 2208 - 2211
[47] Implementation of Energy Efficient FIR Gaussian Filter on FPGA
Anand, Vatsala
Kaur, Amanpreet
PROCEEDINGS OF 4TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING, COMPUTING AND CONTROL (ISPCC 2K17), 2017, : 431 - 435
[48] EFFICIENT FIR FILTER ARCHITECTURES SUITABLE FOR FPGA IMPLEMENTATION
EVANS, JB
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1994, 41 (07): : 490 - 493
[49] FIR Filter Design Based On FPGA
Zheng Jiayu
Wei Zhenhua
2018 10TH INTERNATIONAL CONFERENCE ON MEASURING TECHNOLOGY AND MECHATRONICS AUTOMATION (ICMTMA), 2018, : 36 - 40
[50] Design of FIR filter based on FPGA
Sun Chao
Qi Hui
Su Tong
Ma Junzhi
Zhu Yongjie
Ding Jianjun
PROCEEDINGS OF 2020 IEEE 4TH INFORMATION TECHNOLOGY, NETWORKING, ELECTRONIC AND AUTOMATION CONTROL CONFERENCE (ITNEC 2020), 2020, : 1691 - 1694

← 1 2 3 4 5 →