Interface Trap Density of Commercial 1.7 kV SiC Power MOSFETs

被引：1
|
作者：
Spejo, Lucas B. [1 ,2 ]
Lucidi, Samuel
Puydinger dos Santos, Marcos V. [1 ,2 ]
Diniz, Jose A. [1 ,2 ]
Minamisawa, Renato A.
机构：
[1] Univ Estadual Campinas, Sch Elect & Comp Engn, Campinas, Brazil
[2] Univ Appl Sci & Arts Northwestern Switzerland, Inst Elect Power Syst, Windisch, Switzerland
来源：
2023 37TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES, SBMICRO | 2023年
关键词：
Silicon carbide (SiC); power MOSFET; interface traps; subthreshold slope; threshold voltage; oxide reliability; C-V curve;
D O I：
10.1109/SBMicro60499.2023.10302591
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The gate oxide interface traps strongly influence the device threshold voltage stability, channel mobility and reliability. This paper characterizes the interface trap density from commercial state-of-the-art 1.7 kV SiC MOSFETs. The subthreshold slope method was used to extract the interface trap density, and C-V curves were performed to add insight into the oxide charges. The devices presented an interface trap density of around 10(13) cm(-2) eV(-1) near the conduction band edge and interface states distributed along the bandgap. These results provide essential information on the gate oxide reliability status of such commercial devices under consideration for industrial and photovoltaic applications.
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页数：4
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