2?s row time 12-bit column-parallel single slope ADC for high-speed CMOS image sensor

To improve the conversion speed of single-slope (SS) analog-to-digital converter (ADC) for high frame rate CMOS image sensor, a cycle time-to-digital converter (TDC)-based readout technique is proposed, which optimizes the quantization method. And the proposed SS ADC prioritizes the quantization of the most significant bit (MSB), aiming to shorten the search range of the slope and greatly improve the quantization speed while ensuring accuracy. Furthermore, the proposed scheme is reversible to operate the conventional SS ADC algorithm, thus it preserves the structural advantages of the SS ADC. The proposed SS ADC is designed and simulated with 0.11-mu m process. The simulation results show that the row time of SS ADC is 2 mu s and the resolution is 500 ps, which greatly improves the quantization speed while ensuring power consumption and accuracy. The FoM is 182.6 fJ/ step, which is a 7.1% improvement compared to other TDC-based SS ADCs. The proposed SS ADC becomes more effective as the bit-depth of the ADC increases.