CNNET: A Configurable Hardware Accelerator for Efficient Inference of 8-bit Fixed-Point CNNs

被引:0
|
作者
Agbalessi, Christie [1 ]
Indovina, Mark A. [1 ]
机构
[1] Rochester Inst Technol, Dept Elect & Microelect Engn, Rochester, NY 14623 USA
关键词
Convolutional neural network; hardware accelerator; fixed-point networks; Verilog;
D O I
10.1109/SOCC58585.2023.10257082
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Fast, reliable, efficient, and low-cost hardware is essential for the development of autonomous vehicles. To enable safe decision making, artificial intelligence tasks are run to decode a car's environment, including visual and auditive obstacles. Convolutional Neural Networks (CNNs) are the preferred choice due to their scalability and performance. This study focuses on designing a configurable CNN hardware accelerator in Verilog for 8-bit fixed-point networks. The accelerator, CNNET, is intended to improve an existing accelerator, IANET, by increasing the throughput while reducing power consumption and area utilization. IANET is a combination of two accelerators for a fixed data path, while the enhanced accelerator can be scaled to multiple CNN architectures. CNNET accelerator has been verified with a SystemVerilog testbench and Python model, and tested with audio and image CNNs specific to autonomous driving. Compared to IANET, CNNET demonstrates significant enhancements in computational speed, power consumption, area utilization, and memory footprint. It can process 30 images and one audio frame per second at 243 MHz.
引用
收藏
页码:196 / 201
页数:6
相关论文
共 34 条