DaeMon: Architectural Support for Efficient Data Movement in Fully Disaggregated Systems

被引:9
|
作者
Giannoula, Christina [1 ,2 ]
Huang, Kailong [1 ]
Tang, Jonathan [1 ]
Koziris, Nectarios [2 ]
Goumas, Georgios [2 ]
Chishti, Zeshan [3 ]
Vijaykumar, Nandita [1 ]
机构
[1] Univ Toronto, Toronto, ON, Canada
[2] Natl Tech Univ Athens, Athens, Greece
[3] Intel Corp, Mountain View, CA USA
关键词
data movement; data access; memory access; hardware support; hardware mechanism; high performance; memory systems; memory disaggregation; resource disaggregation; disaggregated systems; workload characterization; benchmarking; performance characterization;
D O I
10.1145/3579445
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Resource disaggregation offers a cost effective solution to resource scaling, utilization, and failure-handling in data centers by physically separating hardware devices in a server. Servers are architected as pools of processor, memory, and storage devices, organized as independent failure-isolated components interconnected by a high-bandwidth network. A critical challenge, however, is the high performance penalty of accessing data from a remote memory module over the network. Addressing this challenge is difficult as disaggregated systems have high runtime variability in network latencies/bandwidth, and page migration can significantly delay critical path cache line accesses in other pages. This paper conducts a characterization analysis on different data movement strategies in fully disaggregated systems, evaluates their performance overheads in a variety of workloads, and introduces DaeMon, the first software-transparent mechanism to significantly alleviate data movement overheads in fully disaggregated systems. First, to enable scalability to multiple hardware components in the system, we enhance each compute and memory unit with specialized engines that transparently handle data migrations. Second, to achieve high performance and provide robustness across various network, architecture and application characteristics, we implement a synergistic approach of bandwidth partitioning, link compression, decoupled data movement of multiple granularities, and adaptive granularity selection in data movements. We evaluate DaeMon in a wide variety of workloads at different network and architecture configurations using a state-of-the-art simulator. DaeMon improves system performance and data access costs by 2.39x and 3.06x, respectively, over the widely-adopted approach of moving data at page granularity.
引用
收藏
页数:35
相关论文
共 50 条
  • [41] NeuMMU: Architectural Support for Efficient Address Translations in Neural Processing Units
    Hyun, Bongjoon
    Kwon, Youngeun
    Choi, Yujeong
    Kim, John
    Rhu, Minsoo
    TWENTY-FIFTH INTERNATIONAL CONFERENCE ON ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS (ASPLOS XXV), 2020, : 1109 - 1124
  • [42] Architectural support for multimedia data streams in a descriptor computer: HISC
    Tang, KC
    Fong, AS
    Wu, AKM
    10TH INTERNATIONAL CONFERENCE ON COMPUTER APPLICATIONS IN INDUSTRY AND ENGINEERING, 1997, : 164 - 167
  • [43] Lease/Release: Architectural Support for Scaling Contended Data Structures
    Haider, Syed Kamran
    Hasenplaugh, William
    Alistarh, Dan
    ACM SIGPLAN NOTICES, 2016, 51 (08) : 201 - 212
  • [44] SpZip: Architectural Support for Effective Data Compression In Irregular Applications
    Yang, Yifan
    Emer, Joel S.
    Sanchez, Daniel
    2021 ACM/IEEE 48TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2021), 2021, : 1069 - 1082
  • [45] ARCHITECTURAL SUPPORT FOR SINGLE ADDRESS SPACE OPERATING-SYSTEMS
    KOLDINGER, EJ
    CHASE, JS
    EGGERS, SJ
    SIGPLAN NOTICES, 1992, 27 (09): : 175 - 186
  • [46] An architectural model to support adaptive software systems for sensor networks
    Kim, HC
    Choi, HJ
    Ko, IY
    11TH ASIA-PACIFIC SOFTWARE ENGINEERING CONFERENCE, PROCEEDINGS, 2004, : 670 - 677
  • [47] Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems
    Antonio Clemente, Juan
    Gran, Ruben
    Chocano, Abel
    del Prado, Carlos
    Resano, Javier
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (02) : 530 - 543
  • [48] QUALITY MANAGEMENT SYSTEMS: PROPOSAL ARCHITECTURAL INFORMATION TO SUPPORT A HOSPITAL
    Freixo, Jorge
    Rocha, Alvaro
    SISTEMAS E TECHNOLOGIAS DE INFORMACAO: ACTAS DA 4A CONFERENCIA IBERICA DE SISTEMAS E TECNOLOGIAS DE LA INFORMACAO, 2009, : 349 - 354
  • [49] Architectural support for greater predictability in real-time systems
    Gopalakrishnan, Sathish
    2009 IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING, VOLS 1 AND 2, 2009, : 993 - 993
  • [50] Virtual Shuffling for Efficient Data Movement in MapReduce
    Yu, Weikuan
    Wang, Yandong
    Que, Xinyu
    Xu, Cong
    IEEE TRANSACTIONS ON COMPUTERS, 2015, 64 (02) : 556 - 568