Optimization of Performance Parameters of Phase Frequency Detector Using Taguchi DoE and Pareto ANOVA Techniques

This paper utilizes Taguchi design of experiments and Pareto analysis of variance statistical approaches to demonstrate circuit optimization. The phase-frequency detector (PFD) circuit based on dynamic logic has been chosen for optimization. For various MOSFETs of PFD, three levels and three factors of power supply and width of PMOS and NMOS (V-DD, w(p), and w(n)) are considered to be critical performance governing factors. The Taguchi technique determines the level of significance of a factor that influences a given performance parameter. The crucial factor for a given response is determined via ANOVA analysis. The optimum values for the parameters V-DD, w(p), and w(n )are likewise determined using this procedure to maximize the circuit's overall performance. Taguchi DoE and Pareto Anova analyses have been performed using the Minitab software. Simulating the circuit with GPDK 180nm CMOS technology using these methods ensures that the acquired parameters are correct for best performance. The Cadence Virtuoso tool has been used to conduct pre-layout and post-layout simulations. The simulation outcomes are reasonably close to the ANOVA predicted result. Phase noise, power dissipation, and frequency of operation of the proposed PFD are -159.56dBc/Hz, 9.83 mu W, and 10.21GHz, respectively, and it occupies a chip area of 300.41 mu m(2). The proposed PFD is used to implement a charge-pump PLL which performs effectively with a settling time of 2.59 mu s.