Operation Scheme Optimization for Charge Trap Transistors (CTTs) Based on Fully Depleted Silicon-on-Insulator (FDSOI) Platform

被引：1

作者：

Wang, Wannian ^{[1
]}

Chen, Bing ^{[1
]}

Zhao, Jiayi ^{[1
]}

Loubriat, Sebastien ^{[2
]}

Besnard, Guillaume ^{[3
]}

Maleville, Christophe ^{[3
]}

Weber, Olivier ^{[4
]}

Cheng, Ran ^{[1
]}

机构：

[1] Zhejiang Univ, Sch Micro Nano Elect, Hangzhou, Peoples R China

[2] MINATEC, CEA LETI, 17 rue Martyrs, F-38054 Grenoble 9, France

[3] SOITEC, Parc Technolog Fontaines, F-38190 Bernin, France

[4] STMicroelectronics, 850 Rue Jean Monnet, F-38926 Crolles, France

来源：

2023 7TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE, EDTM | 2023年

基金：

中国国家自然科学基金;

关键词：

charge trapping transistors; embedded non-volatile memory; operation scheme; reliability; and hot carrier injection;

D O I：

10.1109/EDTM55494.2023.10103101

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Recently, the charge trap transistors (CTTs) based on CMOS logic devices have been actively explored. The charges in the CTT gate stack could be injected by the hot carrier (HC) effect and removed by changing the polarity of the gate electric field, which can be used as the "program" and "erase" operations for memory applications. In this work, the performance of the FDSOI CTT under various program voltages has been investigated. It is found that when the devices are under moderate horizontal acceleration (the bias voltage V-D = 1/2VG), the CTT shows better performance uniformity and reliability. In addition, the related working mechanism and an optimized operation scheme have also been proposed.

引用

页数：3

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