A 7-27 GHz DSCL divide-by-2 frequency divider

被引：0

作者：

郭婷 ^{[1
,2
,3
]}

李智群 ^{[1
,2
,3
]}

李芹 ^{[1
,3
]}

王志功 ^{[1
,3
]}

机构：

[1] Institute of RF- & OE-ICs,Southeast University

[2] School of Integrated Circuits,Southeast University

[3] Engineering Research Center of RF-ICs and RF-Systems,Ministry of Education,Nanjing

来源：

半导体学报 | 2012年 / 33卷 / 10期

基金：

中国国家自然科学基金;

关键词：

broadband; frequency divider; dynamic source-coupled logic; dynamic-loading; input-sensitivity; CMOS;

D O I：

暂无

中图分类号：

TN772 [分频器];

学科分类号：

080902 ;

摘要：

This paper presents the design and analysis of a high speed broadband divide-by-2 frequency divider. The proposed divider is a dynamic source-coupled logic（DSCL） structure formed with two dynamic-loading master-slave D latches,which enables high frequency operation and low power consumption.This divider exhibits a wide locking range from 7-27 GHz and the minimum power consumption is only 1.22 mW from a 1.2 V supply.The input sensitivity is as low as -25.4 dBm across the operating frequency range.This chip occupies 685×430μm;area with two on-chip spiral inductors in 90 nm CMOS process.

引用

页码：92 / 96

页数：5

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