A High-Performance FPGA-Based RoCE v2 RDMA Packet Parser and Generator

被引：1
|
作者：
Sun, Zezheng [1 ,2 ]
Guo, Zhichuan [1 ,2 ]
Ma, Jiandong [1 ,2 ]
Pan, Yipeng [1 ,2 ]
机构：
[1] Chinese Acad Sci, Inst Acoust, Natl Network New Media Engn Res Ctr, 21 North Fourth Ring Rd, Beijing 100190, Peoples R China
[2] Univ Chinese Acad Sci, Sch Elect Elect & Commun Engn, 19 A Yuquan Rd, Beijing 100049, Peoples R China
来源：
ELECTRONICS | 2024年 / 13卷 / 20期
关键词：
FPGA; RDMA; RoCE v2; packet parser; packet generator;
D O I：
10.3390/electronics13204107
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
RDMA (Remote Direct Memory Access) technology has been widely applied due to its high-throughput and low-latency characteristics compared with traditional networks. Implementing RDMA with an FPGA (Field-Programmable Gate Array) is a feasible solution. This paper proposes an implementation method for the ROCE v2 (Remote Direct Memory Access) protocol packet parser and generator based on an FPGA, capable of supporting various transaction packet types, such as RDMA READ, RDMA WRITE, and SEND, under the Reliable Connection service. The RDMA READ and RDMA WRITE performance of RDMA is close to 100 Gbps, which provides a feasible solution for the application of wide-area networks.
引用
收藏
页数：16
相关论文
共 50 条
  • [31] FPGA-based hardware accelerator for high-performance data-stream processing
    Lysakov K.F.
    Shadrin M.Y.
    Pattern Recognition and Image Analysis, 2013, 23 (1) : 26 - 34
  • [32] FPGA-Based High-Performance Data Compression Deep Neural Network Accelerator
    Wang, Hanze
    Fu, Yingxun
    Ma, Li
    2022 INTERNATIONAL CONFERENCE ON BIG DATA, INFORMATION AND COMPUTER NETWORK (BDICN 2022), 2022, : 563 - 569
  • [33] A New High-Performance Scalable Dynamic Interconnection for FPGA-based Reconfigurable Systems
    Jovanovic, Slavisa
    Tanougast, Camel
    Weber, Serge
    2008 INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, 2008, : 61 - 66
  • [34] High-performance computing for SKA transient search: Use of FPGA-based accelerators
    Aafreen, R.
    Abhishek, R.
    Ajithkumar, B.
    Vaidyanathan, Arunkumar M.
    Barve, Indrajit V.
    Bhattramakki, Sahana
    Bhat, Shashank
    Girish, B. S.
    Ghalame, Atul
    Gupta, Y.
    Hayatnagarkar, Harshal G.
    Kamini, P. A.
    Karastergiou, A.
    Levin, L.
    Madhavi, S.
    Mekhala, M.
    Mickaliger, M.
    Mugundhan, V.
    Naidu, Arun
    Oppermann, J.
    Pandian, B. Arul
    Patra, N.
    Raghunathan, A.
    Roy, Jayanta
    Sethi, Shiv
    Shaw, B.
    Sherwin, K.
    Sinnen, O.
    Sinha, S. K.
    Srivani, K. S.
    Stappers, B.
    Subrahmanya, C. R.
    Prabu, Thiagaraj
    Vinutha, C.
    Wadadekar, Y. G.
    Wang, Haomiao
    Williams, C.
    JOURNAL OF ASTROPHYSICS AND ASTRONOMY, 2023, 44 (01)
  • [35] High-performance computing for SKA transient search: Use of FPGA-based accelerators
    R. Aafreen
    R. Abhishek
    B. Ajithkumar
    Arunkumar M. Vaidyanathan
    Indrajit V. Barve
    Sahana Bhattramakki
    Shashank Bhat
    B. S. Girish
    Atul Ghalame
    Y. Gupta
    Harshal G. Hayatnagarkar
    P. A. Kamini
    A. Karastergiou
    L. Levin
    S. Madhavi
    M. Mekhala
    M. Mickaliger
    V. Mugundhan
    Arun Naidu
    J. Oppermann
    B. Arul Pandian
    N. Patra
    A. Raghunathan
    Jayanta Roy
    Shiv Sethi
    B. Shaw
    K. Sherwin
    O. Sinnen
    S. K. Sinha
    K. S. Srivani
    B. Stappers
    C. R. Subrahmanya
    Thiagaraj Prabu
    C. Vinutha
    Y. G. Wadadekar
    Haomiao Wang
    C. Williams
    Journal of Astrophysics and Astronomy, 44
  • [36] FPGA-based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data
    Roy, Sujoy Sinha
    Turan, Furkan
    Jarvinen, Kimmo
    Vercauteren, Frederik
    Verbauwhede, Ingrid
    2019 25TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA), 2019, : 387 - 398
  • [37] A high-performance FPGA-based BWA-MEM DNA sequence alignment
    Pham-Quoc, Cuong
    Kieu-Do, Binh
    Thinh, Tran Ngoc
    CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 2021, 33 (02):
  • [38] HIGH-PERFORMANCE FPGA-BASED FLOATING-POINT ADDER WITH THREE INPUTS
    Guntoro, Andre
    Glesner, Manfred
    2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2, 2008, : 626 - 629
  • [39] A High-Performance FPGA-based LDPC Decoder for Solid-State Drives
    Liu, Yanhuan
    Zhang, Chun
    Song, Pengcheng
    Jiang, Hanjun
    2017 IEEE 60TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2017, : 1232 - 1235
  • [40] A High-Performance and Accurate FPGA-Based Flow Monitor for 100 Gbps Networks
    Sha, Meng
    Guo, Zhichuan
    Wang, Ke
    Zeng, Xuewen
    ELECTRONICS, 2022, 11 (13)
12345