A High-Performance FPGA-Based RoCE v2 RDMA Packet Parser and Generator

被引：1
|
作者：
Sun, Zezheng [1 ,2 ]
Guo, Zhichuan [1 ,2 ]
Ma, Jiandong [1 ,2 ]
Pan, Yipeng [1 ,2 ]
机构：
[1] Chinese Acad Sci, Inst Acoust, Natl Network New Media Engn Res Ctr, 21 North Fourth Ring Rd, Beijing 100190, Peoples R China
[2] Univ Chinese Acad Sci, Sch Elect Elect & Commun Engn, 19 A Yuquan Rd, Beijing 100049, Peoples R China
来源：
ELECTRONICS | 2024年 / 13卷 / 20期
关键词：
FPGA; RDMA; RoCE v2; packet parser; packet generator;
D O I：
10.3390/electronics13204107
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
RDMA (Remote Direct Memory Access) technology has been widely applied due to its high-throughput and low-latency characteristics compared with traditional networks. Implementing RDMA with an FPGA (Field-Programmable Gate Array) is a feasible solution. This paper proposes an implementation method for the ROCE v2 (Remote Direct Memory Access) protocol packet parser and generator based on an FPGA, capable of supporting various transaction packet types, such as RDMA READ, RDMA WRITE, and SEND, under the Reliable Connection service. The RDMA READ and RDMA WRITE performance of RDMA is close to 100 Gbps, which provides a feasible solution for the application of wide-area networks.
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页数：16
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