Energy Efficient Approximate Multiplier for Image Processing Applications

Approximate multipliers have paved the way for high-speed and energy-efficient applications with reduction in area, power consumption and delay. This is generally achieved with a slight compromise in computational accuracy. This study presents two novel imprecise 4:2 compressors which are used for implementing 8 x 8 Dadda multipliers. These compressors incorporate an input reordering circuit which increases the accuracy as well as reduces the hardware complexity at the same time. The efficiency of these approximate multipliers, constructed using the novel compressors, is extensively evaluated against different implementation and accuracy parameters. On average, the proposed multipliers achieve a 20.19 % reduction in power delay product (PDP), with error rates of approximately 26.67 % and 74.66 % compared to an accurate multiplier. Additionally, they demonstrate superior circuit performance optimization as compared to the state-of-the-art approximate multipliers. Simulation results in terms of Mean Structural Similarity Index Measure (MSSIM) for different image processing applications, show that the proposed multipliers maintain an average structural similarity of 97.59 % compared to exact multipliers.