共 50 条
- [41] Multi-valued logic design methodology with double negative differential resistance transistors MICRO & NANO LETTERS, 2017, 12 (10): : 738 - 743
- [42] A novel current-mode design scheme for multi-valued logic gates 2002 23RD INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS, 2002, : 609 - 612
- [43] An Alternative Approach to the Revision of Ordinal Conditional Functions in the Context of Multi-Valued Logic ARTIFICIAL NEURAL NETWORKS-ICANN 2010, PT II, 2010, 6353 : 200 - 203
- [46] A CMOS current-mode full-adder cell for multi-valued logic VLSI 40TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 1998, : 463 - 467
- [47] Implementation of Multi-Valued Logic Gates Using Full Current-Mode CMOS Circuits Analog Integrated Circuits and Signal Processing, 2004, 39 : 191 - 204
- [49] A New Logic Optimization Algorithm of Multi-valued Logic Function Based on Two-valued Logic FRONTIERS OF MANUFACTURING AND DESIGN SCIENCE II, PTS 1-6, 2012, 121-126 : 4330 - +
- [50] A Mature Methodology for Implementing Multi-Valued Logic in Silicon 38TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2008), 2008, : 2 - 7