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- [21] FPGA-based Implementation of the Stereo Matching Algorithm using High-Level Synthesis 2021 IEEE 14TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANY-CORE SYSTEMS-ON-CHIP (MCSOC 2021), 2021, : 1 - 7
- [22] FPGA-Based Acceleration of Expectation Maximization Algorithm using High-Level Synthesis 2019 CONFERENCE ON DESIGN AND ARCHITECTURES FOR SIGNAL AND IMAGE PROCESSING (DASIP), 2019, : 41 - 46
- [23] High-level synthesis compile optimization algorithm for recursive functions Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics, 2013, 25 (10): : 1557 - 1565
- [24] A thread partitioning algorithm in low power high-level synthesis ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2004, : 74 - 79
- [25] An integrated algorithm for memory allocation and assignment in high-level synthesis 39TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2002, 2002, : 608 - 611
- [26] A Software Pipelining Algorithm in High-Level Synthesis for FPGA Architectures ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2, 2009, : 297 - +
- [29] A Binding Algorithm in High-Level Synthesis for Path Delay Testability 2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2013, : 546 - 551
- [30] An evolutionary algorithm for the testable allocation problem in high-level synthesis ICES 2002: 9TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-111, CONFERENCE PROCEEDINGS, 2002, : 471 - 474