Wafer-level chip-scale package favors small-form-factor ASICS

被引：0
|
作者：
Allan, Roger
机构：
来源：
Electronic Design | 2004年 / 52卷 / 09期
关键词：
Application specific integrated circuits - Approximation theory - Ball grid arrays;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
A fully qualified, high-performance, low-power, and small-form-factor wafer-level chip scale package (W-CSP) has been developed by Oki Semiconductor. The product is available in BGA- and LGA-type styles, and targets chip sizes from 2 by 2 mm up to 8 by 8 mm with pin counts up to 250 pins. The package has the same pin count of other packages, yet it is half the size of a fine-pitch BGA package and one-fourth the size of a fine-pitch QFP package. The W-CSP, which is made up of a molded halogen-free resin with a thickness as small as 0.4 mm, the package has a reliability rating equivalent to conventional packages.
引用
收藏
相关论文
共 50 条
  • [31] Gold embrittlement of solder joints in wafer-level chip-scale package on printed circuit board with Ni/Au surface finish
    Huang, Xingjia
    Lee, S. W. Ricky
    Li, Ming
    Chen, William T.
    IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, 2008, 31 (03): : 185 - 191
  • [32] Effect of local grain distribution and Enhancement on edgebond applied wafer-level chip-scale package (WLCSP) thermal cycling performance
    Lee, Tae-Kyu
    Xie, Weidong
    Perng, Steven
    Ibe, Edward
    Loh, Karl
    2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2016, : 1502 - 1508
  • [33] A 5.2 GHz CMOS low noise amplifier with high-Q inductors embedded in wafer-level chip-scale package
    Fukuda, Satoshi
    Ito, Hiroyuki
    Itoi, Kazuhisa
    Sato, Masakazu
    Ito, Tatsuya
    Yamauchi, Ryozo
    Okada, Kenichi
    Masu, Kazuya
    2007 IEEE INTERNATIONAL WORKSHOP ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY, PROCEEDINGS: ENABLING TECHNOLOGIES FOR EMERGING WIRELESS SYSTEMS, 2007, : 34 - +
  • [34] Structural design optimization for board-level drop reliability of wafer-level chip-scale packages
    Tsai, Tsung-Yueh
    Lai, Yi-Shao
    Yeh, Chang-Lin
    Chen, Rong-Sheng
    MICROELECTRONICS RELIABILITY, 2008, 48 (05) : 757 - 762
  • [35] Redistribution Layer Routing for Integrated Fan-Out Wafer-Level Chip-Scale Packages
    Lin, Bo-Qiao
    Lin, Ting-Chou
    Chang, Yao-Wen
    2016 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2016,
  • [36] How buffer layers can provide stress management for wafer-level chip-scale packages
    Kunselman, M
    Larson, L
    Alger, J
    Ranjan, M
    Zafiropoulo, S
    SOLID STATE TECHNOLOGY, 2004, 47 (08) : 53 - +
  • [37] Innovative Methodologies of Circuit Edit on Wafer-level Chip Scale Package (WLCSP) Devices
    Liu, Shih-Ting
    Liu, Tao-Chi
    Chang, Ming-Lun
    Lin, Jandel
    ISTFA 2010: CONFERENCE PROCEEDINGS FROM THE 36TH INTERNATIONAL SYMPOSIUM FOR TESTING AND FAILURE ANALYSIS, 2010, : 359 - 363
  • [38] Wafer-level integration of micro heaters on an alkali vapor cell for chip-scale atomic magnetometers
    Li, Guoliang
    Shang, Jintang
    Zhang, Jin
    Ji, Yu
    2018 19TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2018, : 1564 - 1567
  • [39] Topological and Functional Partitioning in EM Analysis: Application to Wafer-Level Chip-Scale Harmonic Filters
    Wane, Sidina
    Rautio, James C.
    Muehlhaus, Volker
    2009 IEEE/MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM, VOLS 1-3, 2009, : 1621 - +
  • [40] Wafer-level chip size package (WL-CSP)
    Töpper, M
    Fehlberg, S
    Scherpinski, K
    Karduck, C
    Glaw, V
    Heinricht, K
    Coskina, P
    Ehrmann, O
    Reichl, H
    IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2000, 23 (02): : 233 - 238
12345