Cost-effective design for MPEG2 audio decoder with embedded RISC core

被引：0
|
作者：
Tsai, Tsung-Han [1 ]
Chen, Liang-Gee [1 ]
Wu, Ren-Jr [1 ]
机构：
[1] Fu Jen Univ, Taipei, Taiwan
来源：
IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 1999年
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：361 / 369
相关论文
共 50 条
  • [41] Software optimization of the MPEG-audio decoder using a 32-bit MCU RISC processor
    Lee, KS
    Park, YC
    Youn, DH
    2002 INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS, DIGEST OF TECHNICAL PAPERS, 2002, : 330 - 331
  • [42] A cost-effective VLSI architecture of VLD for MPEG-2 and AVS
    Qu, Yanmei
    Li, Yu
    He, Yun
    Mei, Shunliang
    2007 IEEE INTERNATIONAL CONFERENCE ON MULTIMEDIA AND EXPO, VOLS 1-5, 2007, : 1619 - 1622
  • [43] An efficient memory arbitration algorithm for a single chip MPEG2 AV decoder
    Takizawa, T
    Hirasawa, M
    ICCE: 2001 INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS, DIGEST OF TECHNICAL PAPERS, 2001, : 182 - 183
  • [44] Software optimization of the MPEG-AUDIO decoder using a 32-bit MCU RISC processor
    Lee, KS
    Park, YC
    Youn, DH
    IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 2002, 48 (03) : 671 - 676
  • [45] Embedded software optimization for MP3 decoder implemented on RISC core
    Yao, YB
    Yao, QD
    Liu, P
    Xiao, ZB
    IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 2004, 50 (04) : 1244 - 1249
  • [46] A system level integration design for MPEG Layer III audio decoder
    Tsai, TH
    2000 5TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING PROCEEDINGS, VOLS I-III, 2000, : 1333 - 1336
  • [47] A high-speed memory interface architecture for MPEG2 video decoder
    Jia Xiaoling
    Chen Guanghua
    Zou Weiyu
    PROCEEDINGS OF THE SEVENTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN, PACKAGING AND FAILURE ANALYSIS (HDP'05), 2005, : 538 - 541
  • [48] MPEG-2 AAC 5.1-Channel Decoder Software for a Low-Power Embedded RISC Microprocessor
    Yuichiro Takamizawa
    Kouhei Nadehara
    Max Boegli
    Masao Ikekawa
    Ichiro Kuroda
    Journal of VLSI signal processing systems for signal, image and video technology, 2001, 29 : 247 - 254
  • [49] MPEG-2 AAC 5.1-channel decoder software for a low-power embedded RISC microprocessor
    Takamizawa, Y
    Nadehara, K
    Boegli, M
    Ikekawa, M
    Kuroda, I
    JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2001, 29 (03): : 247 - 254
  • [50] A Cost-Effective Tag Design for Memory Data Authentication in Embedded Systems
    Hong, Mei
    Guo, Hui
    Hu, X. Sharon
    CASES'12: PROCEEDINGS OF THE 2012 ACM INTERNATIONAL CONFERENCE ON COMPILERS, ARCHITECTURES AND SYNTHESIS FOR EMBEDDED SYSTEMS, 2012, : 17 - 26
12345