VLSI ARCHITECTURES FOR COMPUTING MULTIPLICATIONS AND INVERSES IN GF(2M).

Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that can be easily realized on VLSI chips. J. L. Massey and J. K. Omura recently (1981) developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2**m ). With the simple squaring property of the normal basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2**m ). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable, and, therefore, naturally suitable for VLSI implementation. 12 refs.