Compiler/hardware co-design for instruction boosting in ILP processors

被引：0
|
作者：
Feng Chia Univ, Taichung, Taiwan [1 ]
机构：
来源：
IEE Proc Comput Digital Tech | / 6卷 / 269-274期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [21] On the Co-Design of Quantum Software and Hardware
    Li, Gushu
    Wu, Anbang
    Shi, Yunong
    Javadi-Abhari, Ali
    Ding, Yufei
    Xie, Yuan
    PROCEEDINGS OF THE 8TH ACM INTERNATIONAL CONFERENCE ON NANOSCALE COMPUTING AND COMMUNICATION (ACM NANOCOM 2021), 2021,
  • [22] Hardware/software co-design for multimedia
    Wolf, W
    ADVANCED SIGNAL PROCESSING: ALGORITHMS, ARCHITECTURES, AND IMPLEMENTATIONS VII, 1997, 3162 : 510 - 517
  • [23] Hardware Software Co-design in Haskell
    Aronsson, Markus
    Sheeran, Mary
    ACM SIGPLAN NOTICES, 2017, 52 (10) : 162 - 173
  • [24] Hierarchical hardware/software co-design
    Niculiu, T
    Burileanu, D
    Manolescu, A
    Becker, J
    Glesner, M
    SIMULATION IN INDUSTRY'99: 11TH EUROPEAN SIMULATION SYMPOSIUM 1999, 1999, : 697 - 699
  • [25] Hardware Development: Agile and Co-Design
    Bertoze Lima, Glaydson Luiz
    Lopes Ferreira, Guilherme Augusto
    Saotome, Osamu
    da Cunha, Adilson Marques
    Vieira Dias, Luiz Alberto
    2015 12TH INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY - NEW GENERATIONS, 2015, : 784 - 787
  • [26] Automatic SoC Design Flow on Many-core Processors: a Software Hardware Co-Design Approach for FPGAs
    Liu, Ling
    Morozov, Oleksii
    Han, Yuxing
    Gutknecht, Juerg
    Hunziker, Patrick
    FPGA 11: PROCEEDINGS OF THE 2011 ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD PROGRAMMABLE GATE ARRAYS, 2011, : 37 - 40
  • [27] Compiler Technologies in Deep Learning Co-Design: A Survey
    Zhang, Hongbin
    Xing, Mingjie
    Wu, Yanjun
    Zhao, Chen
    Intelligent Computing, 2023, 2
  • [28] DSP processor/compiler co-design: A quantitative approach
    Zivojnovic, V
    Pees, S
    Schlager, C
    9TH INTERNATIONAL SYMPOSIUM ON SYSTEMS SYNTHESIS, PROCEEDINGS, 1996, : 108 - 113
  • [29] Scalable hardware memory disambiguation for high ILP processors
    Sethumadhavan, S
    Desikan, R
    Burger, D
    Moore, CR
    Keckler, SW
    36TH INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, PROCEEDINGS, 2003, : 399 - 410
  • [30] Instruction scheduling with release times and deadlines on ILP processors
    Wu, Hui
    Jaffar, Joxan
    Xue, Jingling
    12TH IEEE INTERNATIONAL CONFERENCE ON EMBEDDED AND REAL-TIME COMPUTING SYSTEMS AND APPLICATIONS, PROCEEDINGS, 2006, : 51 - +
12345