共 50 条
- [21] Reliability-aware design flow for silicon photonics on-chip interconnect 1763, Institute of Electrical and Electronics Engineers Inc., United States (22):
- [25] The effect of power islands on Delta-I noise, interconnect noise, and timing for wide, on-chip data-buses Electrical Performance of Electronic Packaging, 2004, : 303 - 306
- [26] AQUAIA: A CAD tool for on-chip interconnect modeling, analysis, and optimization ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 2002, : 337 - 340
- [30] Noise-aware simulation-based sizing and optimization of clocked comparators Analog Integrated Circuits and Signal Processing, 2014, 81 : 723 - 728