On the effectiveness of residue code checking for parallel two's complement multipliers

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Univ of Saarland, Saarbruecken, Germany [1 ]
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IEEE Trans Very Large Scale Integr VLSI Syst | / 2卷 / 227-239期
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Manuscript received September 1; 1994; revised August 25; 1995. This work was supported by DFG under Grant Sp431/1-1 and SFB 124-VLSI Entwurfsmethoden und Parallelitat. This paper was presented in part at the 24th International Symposium on Fault-Tolerant Computing; Austin; TX; June; 1.5-17; 1994. U. Sparmann was with the Department of ECE; University of Iowa; Iowa City; IA 52242 USA. He is now with the Computer Science Department; University of Saarland; D; 6604; 1; Saarbrucken; Germany. S. M. Reddy is with the Department of ECE; IA 52242 USA. Publisher ltem Identifier S 1063-8210(96)04060-7;
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