Area-efficient analog VLSI architecture for state-parallel viterbi decoding

被引：0
|
作者：
John Hopkins Univ, Baltimore, United States [1 ]
机构：
来源：
Proc IEEE Int Symp Circuits Syst | / II-432 - II-435期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
7
引用
收藏
相关论文
共 50 条
  • [1] An area-efficient analog VLSI architecture for state-parallel Viterbi decoding
    He, K
    Cauwenberghs, G
    ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2: ANALOG AND DIGITAL CIRCUITS, 1999, : 432 - 435
  • [2] Vlsi implementation of an area-efficient architecture for the Viterbi algorithm
    Cabrera, C
    Boo, M
    Bruguera, JD
    1997 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I - V: VOL I: PLENARY, EXPERT SUMMARIES, SPECIAL, AUDIO, UNDERWATER ACOUSTICS, VLSI; VOL II: SPEECH PROCESSING; VOL III: SPEECH PROCESSING, DIGITAL SIGNAL PROCESSING; VOL IV: MULTIDIMENSIONAL SIGNAL PROCESSING, NEURAL NETWORKS - VOL V: STATISTICAL SIGNAL AND ARRAY PROCESSING, APPLICATIONS, 1997, : 623 - 626
  • [3] Area-efficient VLSI architecture for the traceback Viterbi decoder supporting punctured codes
    Kim, S
    Hwang, SY
    ELECTRONICS LETTERS, 1996, 32 (08) : 733 - 735
  • [4] An area-efficient VLSI architecture for decoding of Reed-Solomon codes
    Hsu, JM
    Wang, CL
    1996 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, CONFERENCE PROCEEDINGS, VOLS 1-6, 1996, : 3291 - 3294
  • [5] An area-efficient VLSI architecture of the viterbi decoder for reverse link IS-95 (CDMA) air interface
    Mujtaba, SA
    ICSP '98: 1998 FOURTH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING, PROCEEDINGS, VOLS I AND II, 1998, : 525 - 528
  • [6] Area-Efficient Pipelined VLSI Architecture for Polar Decoder
    Tan, Weihang
    Wang, Antian
    Xu, Yunhao
    Lao, Yingjie
    2020 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2020), 2020, : 352 - 357
  • [7] AN AREA-EFFICIENT COLOR DEMOSAICKING SCHEME FOR VLSI ARCHITECTURE
    Shiau, Yeu-Horng
    Chen, Pei-Yin
    Chang, Chia-Wen
    INTERNATIONAL JOURNAL OF INNOVATIVE COMPUTING INFORMATION AND CONTROL, 2011, 7 (04): : 1739 - 1752
  • [8] HIGH-SPEED PARALLEL VITERBI DECODING - ALGORITHM AND VLSI-ARCHITECTURE
    FETTWEIS, G
    MEYR, H
    IEEE COMMUNICATIONS MAGAZINE, 1991, 29 (05) : 46 - 55
  • [9] An efficient reformulation based VLSI architecture for Adaptive Viterbi Decoding in wireless applications
    Gang, Y
    Arslan, T
    Erdogan, A
    2004 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS DESIGN AND IMPLEMENTATION, PROCEEDINGS, 2004, : 206 - 210
  • [10] An area-efficient VLSI architecture for Reed-Solomon decoder
    Guo, YF
    Li, ZC
    Wang, Q
    INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS AND INFORMATION TECHNOLOGIES 2005, VOLS 1 AND 2, PROCEEDINGS, 2005, : 1154 - 1158
12345