State machine design using the set-or-hold method

This paper presents a method for the design of synchronous sequential state machines. The method can be used to write the next state output equations for state machines from a timing diagram, from a state diagram, or from an algorithmic state machine chart. The classification of logic circuits is presented to show where synchronous sequential state machines lie in the realm of logic circuit design. The set-or-hold method involves obtaining the excitation input equations for D-type bistables. After a review of the three types of circuit models for synchronous state machines and the introduction of the synchronous design process, the author applies the set-or-hold method to obtain the next state output equations for three different logic descriptions of Moore, Mealy, and mixed type machines.