Swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications

被引：0

作者：

Toshiba America Electronic, Components, San Jose, United States ^{[1
]}

机构：

来源：

IEEE J Solid State Circuits | / 6卷 / 804-809期

关键词：

D O I：

暂无

中图分类号：

学科分类号：

摘要：

引用

共 48 条

[21] CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications
Sundar, S. Sriram
Mahendran, G.
INTEGRATION-THE VLSI JOURNAL, 2024, 95
[22] Low-power circuit implementation for partial-product addition using pass-transistor logic
Law, CF
Rofail, SS
Yeo, KS
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 1999, 146 (03): : 124 - 129
[23] Novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique
Wang, BT
Kuo, JB
PROCEEDINGS OF THE 43RD IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 2000, : 694 - 697
[24] Single-electron pass-transistor logic with multiple tunnel junctions and its hybrid circuit with MOSFETs
Cho, YK
Jeong, YH
ETRI JOURNAL, 2004, 26 (06) : 669 - 672
[25] Logic-in-memory VLSI circuit for fully parallel nearest pattern matching based on floating-gate-MOS pass-transistor logic
Hanyu, T
Kaeriyama, S
Kameyama, M
JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING, 2005, 11 (5-6) : 619 - 632
[26] A lower-power register file based on complementary pass-transistor adiabatic logic
Hu, JP
Xu, TF
Li, H
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2005, E88D (07) : 1479 - 1485
[27] Design of low power digital VLSI circuits based on a novel Pass-transistor Logic
Song, MK
Asada, K
IEICE TRANSACTIONS ON ELECTRONICS, 1998, E81C (11) : 1740 - 1749
[28] Design of FinFET-based Energy Efficient Pass-Transistor Adiabatic Logic for ultra-low power applications
Bhuvana, B. P.
Bhaaskaran, V. S. Kanchana
MICROELECTRONICS JOURNAL, 2019, 92
[29] An Efficient Power Clock Generation Circuit for Complementary Pass-Transistor Adiabatic Logic Carry-Save Multiplier
Ranjith, P.
Mandal, Sushanta K.
Nagchoudhuri, Dipankar
2009 4TH INTERNATIONAL CONFERENCE ON COMPUTERS AND DEVICES FOR COMMUNICATION (CODEC 2009), 2009, : 92 - 95
[30] Novel Pass-transistor Logic based Ultralow Power Variation Resilient CMOS Full Adder
Guduri, Manisha
Islam, Aminul
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17 (02) : 302 - 317

← 1 2 3 4 5 →