Low-power and low-voltage CMOS digital design

Low-voltage and low-power digital design has to be performed at several levels such as architecture, logic and basic cell levels, while considering activity, capacitance, frequency and supply voltage reduction. Examples of activity and capacitance reduction will be provided for a low-power digital cell library and for gated clock and asynchronous Finite State Machines. Reduction of supply voltage and operating frequency is considered for complex gate decomposition and parallelized logic circuits such as parallelized memories, synchronous counters and shift registers. Reduction of the number of basic operations to execute a given task is illustrated by the design of an efficient 8-bit pipelined microprocessor.