HIGH-SPEED GaAs 16 multiplied by 16-BIT PARALLEL MULTIPLIER.

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作者
Nakayama, Yoshiro
Suyama, Katsuhiko
Shimizu, Haruo
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TN [电子技术、通信技术];
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0809 ;
摘要
The design, fabrication, and performance of the first high-speed GaAs 16 multiplied by 16-bit parallel multiplier produced using tungsten-silicide self-aligned technology are described. This 3168-gate multiplier circuit has a gate length of 2 mu m, a multiply time of 10. 5 ns, and a power dissipation of 952 mW at a supply voltage of 1. 6 V. The projected performance, assuming a gate length of 1 mu m and inherently faster architecture, is for a multiply time of 4 ns.
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页码:417 / 429
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