Removal of redundancy in combinational circuits under classification of undetectable faults

被引：0
|
作者：
Kajihara, Seiji [1 ]
Kinoshita, Kozo [1 ]
Shiba, Haruko [1 ]
机构：
[1] Osaka Univ, Suita, Japan
来源：
Systems and Computers in Japan | 1993年 / 24卷 / 07期
关键词：
12;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：31 / 40
相关论文
共 50 条
  • [41] Simulation and generation of IDDQ tests for bridging faults in combinational circuits
    Chakravarty, S
    Thadikaran, PJ
    IEEE TRANSACTIONS ON COMPUTERS, 1996, 45 (10) : 1131 - 1140
  • [42] Method of diagnosing multiple stuck-at-faults in combinational circuits
    Yamada, Teruhiko
    Hamada, Shuji
    Matsumoto, Tatsuo
    Takahashi, Toshihiko
    Nakayama, Takao
    Systems and Computers in Japan, 1991, 22 (11) : 21 - 30
  • [43] A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits
    El-Maleh, Aiman H.
    Oughali, Feras Chikh
    MICROELECTRONICS RELIABILITY, 2014, 54 (01) : 316 - 326
  • [44] Combinational Framework for Classification of Bearing Faults in Rotating Machines
    Kumar, Sujit
    Ganga, D.
    JOURNAL OF COMPUTING AND INFORMATION SCIENCE IN ENGINEERING, 2024, 24 (02)
  • [45] New procedures for identifying undetectable and redundant faults in synchronous sequential circuits
    Reddy, Sudhakar M.
    Pomeranz, Irith
    Lin, Xijiang
    Basturkmen, Nadir Z.
    Proceedings of the IEEE VLSI Test Symposium, 1999, : 275 - 281
  • [46] New procedures for identifying undetectable and redundant faults in synchronous sequential circuits
    Reddy, SM
    Pomeranz, I
    Lin, XJ
    Basturkmen, NZ
    17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1999, : 275 - 281
  • [47] On undetectable faults in partial scan circuits using transparent-scan
    Pomeranz, I
    Reddy, SM
    IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS, 2004, : 82 - 84
  • [48] COMBINATIONAL ATPG THEOREMS FOR IDENTIFYING UNTESTABLE FAULTS IN SEQUENTIAL-CIRCUITS
    AGRAWAL, VD
    CHAKRADHAR, ST
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1995, 14 (09) : 1155 - 1160
  • [49] A method of generating tests for marginal delays and delay faults in combinational circuits
    Takahashi, H
    Matsunaga, T
    Boateng, KO
    Takamatsu, Y
    SIXTH ASIAN TEST SYMPOSIUM (ATS'97), PROCEEDINGS, 1997, : 320 - 325
  • [50] Precise test generation for resistive bridging faults of CMOS combinational circuits
    Maeda, T
    Kinoshita, K
    INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS, 2000, : 510 - 519
12345