TECHNIQUE FOR THE DESIGN OF SYSTOLIC ARRAYS WITH BIT-LEVEL PIPELINING.

被引：0

作者：

Madan, B.B. ^{[1
]}

Parker, S.R. ^{[1
]}

Zubair, M. ^{[1
]}

机构：

[1] IIT Delhi, New Delhi, India, IIT Delhi, New Delhi, India

来源：

| 1600年 / 06期

关键词：

BIT-LEVEL PIPELINING - GAIN TRANSFER RULE - SIGNAL CONVOLUTION - SIGNAL FLOW GRAPH - SYSTOLIC ARRAYS;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

引用

共 50 条

[1] A TECHNIQUE FOR THE DESIGN OF SYSTOLIC ARRAYS WITH BIT-LEVEL PIPELINING
MADAN, BB
PARKER, SR
ZUBAIR, M
CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 1987, 6 (02) : 139 - 151
[2] DESIGN OF BIT-LEVEL SYSTOLIC ARRAYS WITH DEPENDENCE GRAPH
LIU, CM
JEN, CW
SYSTOLIC ARRAY PROCESSORS, 1989, : 439 - 448
[3] THE USE OF DATA DEPENDENCE GRAPHS IN THE DESIGN OF BIT-LEVEL SYSTOLIC ARRAYS
MCCANNY, JV
MCWHIRTER, JG
KUNG, SY
IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING, 1990, 38 (05): : 787 - 793
[4] DYNAMIC COMPUTATIONAL BLOCKS FOR BIT-LEVEL SYSTOLIC ARRAYS
JULLIEN, GA
MILLER, WC
GRONDIN, R
DELPUP, L
BIZZAN, SS
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (01) : 14 - 22
[5] BIT-LEVEL SYSTOLIC ARRAYS FOR DIGITAL CONTOUR SMOOTHING
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RECENT ISSUES IN PATTERN ANALYSIS AND RECOGNITION, 1989, 399 : 105 - 120
[6] BIT-LEVEL SYSTOLIC ARRAYS FOR DIGITAL CONTOUR SMOOTHING
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LECTURE NOTES IN COMPUTER SCIENCE, 1989, 399 : 105 - 120
[7] A methodology for testing arbitrary bilateral bit-level systolic arrays
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VLSI DESIGN, 1996, 4 (03) : 257 - 269
[8] EFFICIENT BIT-LEVEL SYSTOLIC ARRAYS FOR INNER PRODUCT COMPUTATION
URQUHART, RB
WOOD, D
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[9] BIT-LEVEL SYSTOLIC ARRAYS FOR FINITE-FIELD MULTIPLICATIONS
WU, CW
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JOURNAL OF VLSI SIGNAL PROCESSING, 1995, 10 (01): : 85 - 92
[10] Data dependence analysis and bit-level systolic arrays of the median filter
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 1998, 8 (08) : 1015 - 1024

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