TECHNIQUE FOR THE DESIGN OF SYSTOLIC ARRAYS WITH BIT-LEVEL PIPELINING.

被引：0
|
作者：
Madan, B.B. [1 ]
Parker, S.R. [1 ]
Zubair, M. [1 ]
机构：
[1] IIT Delhi, New Delhi, India, IIT Delhi, New Delhi, India
来源：
| 1600年 / 06期
关键词：
BIT-LEVEL PIPELINING - GAIN TRANSFER RULE - SIGNAL CONVOLUTION - SIGNAL FLOW GRAPH - SYSTOLIC ARRAYS;
D O I：
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