Design of scan-based low testing power architecture

被引:0
|
作者
Xu, Lei
Sun, Yi-He
Chen, Hong-Yi
机构
关键词
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
相关论文
共 50 条
  • [1] A Novel Scan Architecture for Low Power Scan-Based Testing
    Naeini, Mahshid Mojtabavi
    Ooi, Chia Yee
    VLSI DESIGN, 2015, 2015
  • [2] A scan matrix design for low power scan-based test
    Lin, SP
    Lee, CL
    Chen, JE
    14TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2005, : 224 - 229
  • [3] Scan chain design for shift power reduction in scan-based testing
    LI Jia 1
    2 The Institute of Computing Technology
    ScienceChina(InformationSciences), 2011, 54 (04) : 767 - 777
  • [4] Scan chain design for shift power reduction in scan-based testing
    Jia Li
    Yu Hu
    XiaoWei Li
    Science China Information Sciences, 2011, 54 : 767 - 777
  • [5] Scan chain design for shift power reduction in scan-based testing
    Li Jia
    Hu Yu
    Li XiaoWei
    SCIENCE CHINA-INFORMATION SCIENCES, 2011, 54 (04) : 767 - 777
  • [6] Low-power technique of scan-based design for test
    Xu, L
    Sun, YH
    Chen, HY
    ELECTRONICS LETTERS, 2000, 36 (23) : 1920 - 1921
  • [7] Efficient Partial Scan Cell Gating for Low-Power Scan-Based Testing
    Kavousianos, Xrysovalantis
    Bakalis, Dimitris
    Nikolos, Dimitris
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2009, 14 (02)
  • [8] Scan Cell Reordering Algorithm for Low Power Consumption during Scan-Based Testing
    Kang, Wooheon
    Lim, Hyunyul
    Kang, Sungho
    2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2014, : 300 - 301
  • [9] Efficient scan-based BIST scheme for low power testing of VLSI chips
    Shah, Malav
    ISLPED '06: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, : 376 - 381