共 50 条
- [32] VERTICAL ISOLATION IN SHALLOW n-WELL CMOS CIRCUITS. Electron device letters, 1987, EDL-8 (03): : 107 - 109
- [33] Design of a comparator in a 0.25 μm CMOS technology. PROCEEDINGS OF THE SIXTH WORKSHOP ON ELECTRONICS FOR LHC EXPERIMENTS, 2000, 2000 (10): : 525 - 529
- [35] A BENDING N-WELL BALLAST LAYOUT TO IMPROVE ESD ROBUSTNESS IN FULLY-SILICIDED CMOS TECHNOLOGY 2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2010, : 857 - 860
- [37] LATCH-UP DC TRIGGERING AND HOLDING CHARACTERISTICS OF N-WELL, TWIN-TUB AND EPITAXIAL CMOS TECHNOLOGIES IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS, 1991, 138 (05): : 604 - 612
- [39] Systematic Study of Grounded N-Well Latchup in 55nm Technology 2021 43RD ANNUAL EOS/ESD SYMPOSIUM (EOS/ESD), 2021,