LATCHUP PREVENTION USING AN N-WELL EPI-CMOS PROCESS

被引：4
|
作者：
HOLLY, PJ [1 ]
AKERS, LA [1 ]
机构：
[1] ARIZONA STATE UNIV,DEPT ELECT ENGN,TEMPE,AZ 85281
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 1983年 / 30卷 / 10期
关键词：
D O I：
10.1109/T-ED.1983.21308
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：1403 / 1405
页数：3
相关论文
共 50 条
  • [1] TRANSIENT LATCHUP CHARACTERISTICS IN N-WELL CMOS
    OHZONE, T
    IWATA, H
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1992, 39 (08) : 1870 - 1875
  • [2] LATCHUP PERFORMANCE OF RETROGRADE AND CONVENTIONAL N-WELL CMOS TECHNOLOGIES
    LEWIS, AG
    MARTIN, RA
    HUANG, TY
    CHEN, JY
    KOYANAGI, M
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (10) : 2156 - 2164
  • [3] LATCHUP PERFORMANCE OF RETROGRADE AND CONVENTIONAL N-WELL CMOS TECHNOLOGIES.
    Lewis, Alan G.
    Martin, Russel A.
    Huang, Tiao-Yuan
    Chen, John Y.
    Koyanagi, Mitsumasa
    IEEE Transactions on Electron Devices, 1987, ED-34 (10) : 2156 - 2164
  • [4] Wavelength dependence of transient laser-induced latchup in epi-CMOS test structures
    LaLumondiere, SD
    Koga, R
    Osborn, JV
    Mayer, DC
    Lacoe, RC
    Moss, SC
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2002, 49 (06) : 3059 - 3066
  • [5] N-WELL CMOS PROCESS SPEEDS UP GATE ARRAYS
    GOLD, M
    ELECTRONIC DESIGN, 1981, 29 (24) : 35 - 36
  • [6] A 256K ROM FABRICATED USING N-WELL CMOS PROCESS TECHNOLOGY
    KAMURO, S
    MASAKI, Y
    SANO, K
    KIMURA, S
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1982, 17 (04) : 723 - 726
  • [7] AN N-WELL CMOS DYNAMIC RAM
    SHIMOHIGASHI, K
    MASUDA, H
    KAMIGAKI, Y
    ITOH, K
    HASHIMOTO, N
    ARAI, E
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1982, 29 (04) : 714 - 718
  • [8] A Novel Hybrid RF-DC Converter Using CMOS n-Well Process
    Al-Absi, Munir A.
    Al-Khulaifi, Abdulaziz A.
    IEEE ACCESS, 2024, 12 : 31243 - 31248
  • [9] AN ISOLATED VERTICAL N-P-N TRANSISTOR IN AN N-WELL CMOS PROCESS
    ZEITZOFF, PM
    ANAGNOSTOPOULOS, CN
    WONG, KY
    BRANDT, BP
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (02) : 489 - 494
  • [10] ISOLATED VERTICAL N-P-N TRANSISTOR IN AN N-WELL CMOS PROCESS.
    Zeitzoff, Peter M.
    Anagnostopoulos, Constantine N.
    Wong, Kwok Y.
    Brandt, Brian P.
    IEEE Journal of Solid-State Circuits, 1984, SC-20 (02) : 489 - 494
12345