CMOS pass-gate no-race charge-recycling logic (CPNCL)

被引：0
|
作者：
Yoo, Seung-Moon [1 ]
Kang, Sung-Mo [1 ]
机构：
[1] Univ of Illinois at Urbana-Champaign, Urbana, United States
来源：
Proceedings - IEEE International Symposium on Circuits and Systems | 1999年 / 1卷
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 40 条
  • [31] A 2.5-GHz 860μW charge-recycling fractional-N frequency synthesizer in 130nm CMOS
    Park, Dongmin
    Lee, Wojae
    Jeon, Sehyung
    Cho, ScongHwan
    2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2008, : 88 - 89
  • [32] Study of pass-gate voltage (VPASS) interference in sub-30nm charge-trapping (CT) NAND flash devices
    Hsiao Y.-H.
    Lue H.-T.
    Chang K.-P.
    Hsieh C.-C.
    Hsu T.-H.
    Hsieh K.-Y.
    Lu C.-Y.
    2011 3rd IEEE International Memory Workshop, IMW 2011, 2011,
  • [33] A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic
    Jiang, YB
    Sapatnekar, SS
    Bamji, C
    INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1998, : 276 - 281
  • [34] A 0.5V 200MHz 1-stage 32b ALU using a body bias controlled SOI pass-gate logic
    Fuse, T
    Oowaki, Y
    Yamada, T
    Kamoshida, M
    Ohta, M
    Shino, T
    Kawanaka, S
    Terauchi, M
    Yoshida, T
    Matsubara, G
    Yoshioka, S
    Watanabe, S
    Yoshimi, M
    Ohuchi, K
    Manabe, S
    1997 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - DIGEST OF TECHNICAL PAPERS, 1997, 40 : 286 - 287
  • [35] Low-power motion-vector detection VLSI processor based on pass-gate logic with dynamic supply-voltage/clock-frequency scaling
    Mochizuki, A
    Nishinohara, D
    Hanyu, T
    IEICE TRANSACTIONS ON ELECTRONICS, 2004, E87C (11): : 1876 - 1883
  • [36] A Fully Integrated Multi-Phase Voltage Regulator With Flying-Capacitor-Based Inter-Inductor Current Self-Balancing Scheme and Charge-Recycling Gate Driver
    Cho, Jeong-Hyun
    Bae, Hong-Hyun
    Lim, Gyu-Wan
    Kong, Tae-Hwang
    Yang, Jun-Hyeok
    Kim, Hyun-Sik
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2024, 59 (08) : 2529 - 2544
  • [37] A 5.37mW/Channel Pitch-Matched Ultrasound ASIC with Dynamic-Bit-Shared SAR ADC and 13.2V Charge-Recycling TX in Standard CMOS for Intracardiac Echocardiography
    Lee, Jihee
    Lee, Kyoung-Rog
    Eovino, Benjamin E.
    Park, Jeong Hoan
    Lin, Liwei
    Yoo, Hoi-Jun
    Yoo, Jerald
    2019 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2019, 62 : 190 - U2139
  • [38] A 0.1pJ/b 5-to-10Gb/s Charge-Recycling Stacked Low-Power I/O for On-Chip Signaling in 45nm CMOS SOI
    Liu, Yong
    Hsieh, Ping-Hsuan
    Kim, Seongwon
    Seo, Jae-sun
    Montoye, Robert
    Chang, Leland
    Tierno, Jose
    Friedman, Daniel
    2013 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2013, 56 : 400 - +
  • [39] A 6.5-to-23.3fJ/b/mm Balanced Charge-Recycling Bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with Clock Forwarding and Low-Crosstalk Contraflow Wiring
    Wilson, John M.
    Fojtik, Matthew R.
    Poulton, John W.
    Chen, Xi
    Tell, Stephen G.
    Greer, Thomas H., III
    Gray, C. Thomas
    Dally, William J.
    2016 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2016, 59 : 156 - U210
  • [40] Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High-k-Metal-Gate CMOS Technologies
    Khan, Faraz
    Cartier, Eduard
    Woo, Jason C. S.
    Iyer, Subramanian S.
    IEEE ELECTRON DEVICE LETTERS, 2017, 38 (01) : 44 - 47
1234