共 50 条
- [31] Guest Editors' Introduction - Design and test of core-based systems on chips IEEE DESIGN & TEST OF COMPUTERS, 1997, 14 (04): : 14 - 14
- [32] Design of dynamically assignmentable TAM width for testing core-based SOCs 2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 1399 - +
- [33] Hierarchy-aware and area-efficient test infrastructure design for core-based system chips 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS, 2006, : 283 - +
- [35] Scan chain design for test time reduction in core-based ICs INTERNATIONAL TEST CONFERENCE 1998, PROCEEDINGS, 1998, : 448 - 457
- [36] The design space layer: Supporting early design space exploration for core-based designs DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS, 1999, : 676 - 683
- [37] Multi-Temperature Testing for Core-based System-on-Chip 2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010), 2010, : 208 - 213
- [38] Scalable core-based methodology and synthesizable core for systematic design environment in multicore SoC (MCSoC) 2006 INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING WORKSHOPS, PROCEEDINGS, 2006, : 345 - +
- [39] Quantitative, core-based shape comparison IMAGE PROCESSING - MEDICAL IMAGING 1997, PTS 1 AND 2, 1997, 3034 : 877 - 888
- [40] Architecting voltage islands in core-based System-on-a-Chip designs ISLPED '04: PROCEEDINGS OF THE 2004 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2004, : 180 - 185