IBM POWER6 SRAM arrays

被引：0

作者：

Plass, Donald W. ^{[1
]}

Chan, Yuen H. ^{[1
]}

机构：

[1] IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, NY 12601, United States

来源：

IBM Journal of Research and Development | 2007年 / 51卷 / 06期

关键词：

The IBM POWER6™ microprocessor presented new challenges to array design because of its high-frequency requirement and its use of 65-nm silicon-on-insulator (SOI) technology. Advancements in performance (2X to 3X improvement over the 90-nm generation) and design margins (cell stability; writability; and redundancy coverage) were major focus areas. Key elements of the POWER6 processor chip arrays include paradigm shifts such as thin memory cell layout; large signal read (without a sense amplifier); segmented bitline structure; unclamped column-half-select scheme; multidimensional programmable timing control; and separate elevated static random access memory (SRAM) power supply. There are two main array categories on the POWER6 microprocessor chip: core and nest. Processor core arrays use a single-port; 0.75-μm2; six-transistor (6T) cell and operate at full frequency; whereas the surrounding nest arrays use a smaller 0.65-μm2 cell that operates at half or one-quarter of the core frequency in order to achieve better density and power efficiency. The core arrays include the 96-KB instruction cache (I-cache) and the 64-KB data cache (D-cache); with associate lookup-path SRAM macros. The I-cache is a four-way set-associative; single-port design; whereas the D-cache is an eight-way design with dual read ports to handle multithreading capability. The lookup-path arrays contain content-addressable memory (CAM) and RAM macros with integrated dynamic hit logic circuitry. In the nest portion; an 8-MB level 2 (L2) D-cache and a level 3 (L3) directory (1.2 MB) make up the largest arrays. The latter macro designs use longer bitlines and orthogonal word-decode layouts to achieve high array-area efficiency. © 2007 IBM;

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摘要：

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页码：747 / 756

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