A 3rd order 3bit sigma-delta modulator with reduced delay time of data weighted averaging

被引：0
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作者：
Yi, Soon Jai [1 ]
Kim, Sun-Hong [2 ]
Jeong, Hang-Geun [1 ]
Cho, Seong-Ik [1 ]
机构：
[1] Division of Electronics and Information Engineering, Chonbuk National University, Jeonju, Jeonbuk 561756, Korea, Republic of
[2] Samsung Electro-Mechanics, Suwon, Gyeonggi 443743, Korea, Republic of
来源：
World Academy of Science, Engineering and Technology | 2010年 / 71卷
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页码：539 / 542
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