The potential and the drawbacks of underlap single-gate ultrathin SOI MOSFET

被引：0
|
作者：
Yoshioka, Yoshimasa [1 ]
Hamada, Mitsuo [1 ]
Omura, Yasuhisa [1 ]
机构：
[1] Grad. School of Eng., Kansai University, 3-3-35, Yamate-cho, Suita, Osaka, 564-8680, Japan
来源：
Technology Reports of Kansai University | 2008年 / 50卷
关键词：
18;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：17 / 27
相关论文
共 50 条
  • [41] Impact of different ground planes of UTBB SOI MOSFETs under the single-gate (SG) and double-gate (DG) operation mode
    Othman, Noraini
    Arshad, M. K. Md
    Hashim, S. N. Sabki U.
    2014 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS (ICSE), 2014, : 88 - 91
  • [42] Performance analysis of dielectric modulated underlap FD-SOI MOSFET for biomolecules detection
    Kumar, Saurabh
    Chauhan, R. K.
    APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING, 2022, 128 (12):
  • [43] DIAGNOSIS OF SINGLE-GATE FAILURES IN COMBINATIONAL CIRCUITS
    HORNBUCKLE, GD
    SPANN, RN
    IEEE TRANSACTIONS ON COMPUTERS, 1969, C 18 (03) : 216 - +
  • [44] Analytical model of single-gate silicon-on-insulator (SOI) tunneling field-effect transistors (TFETs)
    Lee, Min Jin
    Choi, Woo Young
    SOLID-STATE ELECTRONICS, 2011, 63 (01) : 110 - 114
  • [45] Effect of Spacer Dielectric of Asymmetric Underlap Double Gate MOSFET on SRAM Performance
    Mishra, Abhijit
    Maity, Subir Kumar
    Dutta, Sayantika
    PROCEEDINGS OF 2ND INTERNATIONAL CONFERENCE ON 2017 DEVICES FOR INTEGRATED CIRCUIT (DEVIC), 2017, : 817 - 820
  • [46] Asymmetric Gate Oxide Thickness Technology for Reduction of Gate Induced Drain Leakage Current in Nanoscale Single Gate SOI MOSFET
    Fathipour, Morteza
    Kohani, Fatemeh
    Ahangari, Zahra
    COMMAD: 2008 CONFERENCE ON OPTOELECTRONIC AND MICROELECTRONIC MATERIALS & DEVICES, 2008, : 136 - 139
  • [47] ANALYSIS OF GATE ENGINEERED SOI MOSFET FOR VLSI APPLICATION
    Ramya, M. S. Annie
    Nirmal, D.
    Soman, Sajitha
    Nair, Prabha P.
    Jeba, Kingsly, I
    2013 IEEE INTERNATIONAL MULTI CONFERENCE ON AUTOMATION, COMPUTING, COMMUNICATION, CONTROL AND COMPRESSED SENSING (IMAC4S), 2013, : 498 - 501
  • [48] The influence of gate underlap on analog and RF performance of III-V heterostructure double gate MOSFET
    Sarkar, Angsuman
    Jana, Rohit
    SUPERLATTICES AND MICROSTRUCTURES, 2014, 73 : 256 - 267
  • [49] COMPARISON OF SINGLE-GATE AND DUAL-GATE FET FREQUENCY DOUBLERS
    GOPINATH, A
    SEEDS, AJ
    RANKIN, JB
    IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 1982, 30 (06) : 919 - 920
  • [50] Analytical threshold voltage model for ultrathin SOI MOSFET's
    Liu, XY
    Sun, HF
    Wu, DX
    SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1 AND 2, PROCEEDINGS, 2001, : 555 - 558
12345