The sampling network for a 16-channel time-interleaved ADC

被引：0

作者：

Ji, Pengfei ^{[1
]}

Liu, Chengyuan ^{[1
]}

Dang, Li ^{[1
]}

Li, Shaoxuan ^{[1
]}

Ding, Ruixue ^{[1
,2
]}

Liu, Shubin ^{[1
,2
]}

Zhu, Zhangming ^{[1
,2
]}

机构：

[1] Xidian Univ, Sch Microelect, Key Lab Analog Integrated Circuits & Syst, Minist Educ, Xian 710071, Peoples R China

[2] Xidian Univ, Hangzhou Inst Technol, Hangzhou 311200, Peoples R China

来源：

MICROELECTRONICS JOURNAL | 2025年 / 156卷

基金：

中国国家自然科学基金;

关键词：

Bootstrapped switch; Sampling network; Source follower; Time-interleaved ADC; SAR ADC;

D O I：

10.1016/j.mejo.2025.106563

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the design of a sampling network for an 8-bit, 16 GS/s, 16-channel time-interleaved analogto-digital converter (ADC) implemented in a 28 nm CMOS process. The network is based on a two-stage resampling architecture. A current-feedback source follower is employed as the buffer, improving the speed and linearity of the buffering stages. Additionally, a novel parallel-path bootstrapped switch is introduced, which significantly enhances the sampling speed. The design also incorporates 4-phase, 4 GHz clocks for the first-stage switches and 16-phase, 1 GHz clocks for the second-stage switches. The entire sampling network occupies an area of 0.2 mm2 and consumes a total power of 63.95 mW. Post-simulation results demonstrate that the sampling network achieves a bandwidth exceeding 9 GHz, with a signal-to-noise plus distortion ratio (SNDR) of 57.6 dB and a spurious-free dynamic range (SFDR) of 62.1 dB at the Nyquist input frequency.

引用

页数：10

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