The sampling network for a 16-channel time-interleaved ADC

This paper presents the design of a sampling network for an 8-bit, 16 GS/s, 16-channel time-interleaved analogto-digital converter (ADC) implemented in a 28 nm CMOS process. The network is based on a two-stage resampling architecture. A current-feedback source follower is employed as the buffer, improving the speed and linearity of the buffering stages. Additionally, a novel parallel-path bootstrapped switch is introduced, which significantly enhances the sampling speed. The design also incorporates 4-phase, 4 GHz clocks for the first-stage switches and 16-phase, 1 GHz clocks for the second-stage switches. The entire sampling network occupies an area of 0.2 mm2 and consumes a total power of 63.95 mW. Post-simulation results demonstrate that the sampling network achieves a bandwidth exceeding 9 GHz, with a signal-to-noise plus distortion ratio (SNDR) of 57.6 dB and a spurious-free dynamic range (SFDR) of 62.1 dB at the Nyquist input frequency.