共 50 条
- [41] A High-Throughput VLSI Architecture Design of Arithmetic Encoder in JPEG2000 Journal of Signal Processing Systems, 2015, 81 : 227 - 247
- [42] Design and Evaluation of Reconfigurable Filters 2017 2ND IEEE INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, SIGNAL PROCESSING AND NETWORKING (WISPNET), 2017, : 2021 - 2026
- [44] A High-Throughput VLSI Architecture Design of Arithmetic Encoder in JPEG2000 JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2015, 81 (02): : 227 - 247
- [46] Memristive Circuit Design of Quantized Convolutional Auto-Encoder IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTATIONAL INTELLIGENCE, 2023, 7 (04): : 1301 - 1313
- [47] ON THE DESIGN OF A DYNAMIC RECONFIGURABLE NETWORK SWITCH MICROPROCESSING AND MICROPROGRAMMING, 1992, 34 (1-5): : 59 - 62
- [49] Reconfigurable RF CMOS Circuit Design for Cognitive Radios 2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009), 2009, : 96 - 99