An inversion/non-inversion dynamic optically reconfigurable gate array VLSI

被引:0
|
作者
Department of Electrical and Electronic Engineering, Shizuoka University, 3-5-1 Johoku, Hamamatsu, Shizuoka 432-8561, Japan [1 ]
机构
来源
WSEAS Trans. Circuits Syst. | 2009年 / 1卷 / 11-20期
关键词
Reconfigurable architectures - Photodiodes - Logic gates - VLSI circuits - Field programmable gate arrays (FPGA) - Reconfigurable hardware;
D O I
暂无
中图分类号
学科分类号
摘要
Up to now, an optically differential reconfigurable gate array taking a differential reconfiguration strategy and a dynamic optically reconfigurable gate array taking a photodiode memory architecture have been proposed. The differential reconfiguration strategy provides a higher reconfiguration frequency, with no increase in laser power, than other optically reconfigurable gate arrays, however the differential reconfiguration strategy can not achieve a high-gate-count VLSI because of the area occupied by the static configuration memory. On the other hand, the photodiode memory architecture can achieve a high-gate-count VLSI, but its configuration is slower than that of the optically differential reconfigurable gate array using equivalent laser power. So, this paper presents a novel inversion/non-inversion dynamic optically reconfigurable gate array VLSI that combines both architectures. It thereby achieves both advantages of rapid configuration and a high gate count. The experiments undertaken in this study clarify the effectiveness of the inversion/non-inversion optical configuration method.
引用
收藏
相关论文
共 50 条
  • [1] Inversion/non-inversion dynamic optically reconfigurable gate array
    Watanabe, Minoru
    Nakajima, Mao
    PROCEEDINGS OF THE 12TH WSEAS INTERNATIONAL CONFERENCE ON CIRCUITS: NEW ASPECTS OF CIRCUITS, 2008, : 249 - +
  • [2] Inversion/non-inversion zero-overhead dynamic optically reconfigurable gate array VLSI
    Kato, Shinichi
    Watanabe, Minoru
    PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, 2008, : 377 - 380
  • [3] Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI
    Kato, Shinichi
    Watanabe, Minoru
    EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, PROCEEDINGS, 2009, 5657 : 139 - 148
  • [4] Inversion/non-inversion reconfiguration scheme for a 0.18 μm CMOS process optically reconfigurable gate array VLSI
    Watanabe, Takahiro
    Watanabe, Minoru
    2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2012, : 117 - 120
  • [5] An 11,424-gate dynamic optically reconfigurable gate array VLSI
    Nakajima, Mao
    Watanabe, Minoru
    PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, 2008, : 293 - 296
  • [6] Dynamic optically reconfigurable gate array
    Department of Systems Innovation and Informatics, Kyushu Institute of Technology, 680-4 Kawazu, Iizuka, Fukuoka 820-8502, Japan
    Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 2006, 45 (4 B): : 3510 - 3515
  • [7] Dynamic optically reconfigurable gate array
    Watanabe, Minoru
    Kobayashi, Fuminori
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2006, 45 (4B): : 3510 - 3515
  • [8] Voltage range evaluation of an optically reconfigurable gate array VLSI
    Shimamura, Yuki
    Watanabe, Minoru
    Watanabe, Nobuya
    2024 IEEE 35TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, ASAP 2024, 2024, : 239 - 240
  • [9] An improved dynamic optically reconfigurable gate array
    Watanabe, M
    Kobayashi, F
    IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: NEW FRONTIERS IN VLSI DESIGN, 2005, : 136 - 141
  • [10] A programmable dynamic optically reconfigurable gate array
    Kubota, Shinya
    Watanabe, Minoru
    2009 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE, 2009, : 332 - 335