Design of multi-FPGAs processor based system for remote sensing image high-speed compression

被引：0

作者：

Xu, Xiaoshen ^{[1
]}

Jiang, Hongxu ^{[1
]}

Xiao, Chaosheng ^{[1
]}

机构：

[1] School of Computer Science and Engineering, Beijing University of Aeronautics and Astronautics, Beijing 100191, China

来源：

Beijing Hangkong Hangtian Daxue Xuebao/Journal of Beijing University of Aeronautics and Astronautics | 2013年 / 39卷 / 03期

关键词：

Integrated circuit design - Remote sensing - Efficiency - Image enhancement - Field programmable gate arrays (FPGA) - Parallel processing systems - System buses - Application programs - Image compression - Software reliability - Digital storage;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

A design of multi-FPGAs for massive remote sensing image high-speed compression was proposed, which includes a hybrid multi-FPGAs based parallel processor architecture due to light coupling between modules and tight association of a single module; a compression mechanism for balanced data distribution and code stream ordered recycling, which improves parallel efficiency of isomorphic FPGAs and ensures correctness of image compression; a processor failure and link failure supported structure fault-tolerant model, which ensures the reliability of compression; a distributed external storage and high-speed serial bus based communication strategy among multi-FPGAs, which satisfies the communication requirements for massive remote sensing image high-speed compression. Experimental result shows: the parallel efficiency of a single processor achieves 93.5%. In this application system, result of hardware compression is consistent with that of software compression, its throughput reaches 1.6 Gbit/s or more and provides high reliability.

引用

页码：361 / 365

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