Efficient self-test design for adders in VLSI

A self-test scheme, under which all test patterns for adder under test in VLSI are produced by the adder self, is presented based on arithmetic additive generator. The patterns are improved with their optimized initial value, and the fault detection and location capabilities are enhanced. The adder self-test is designed with such operations as left shift, logic AND for the test patterns, and so on. Experiments of the self-test for 8-bit, 16-bit, 32-bit ripple carry adder and carry look-ahead adder are performed respectively. And the results show that for the adders with single and couple stuck-at faults, the self-test can implement complete test, and the Fault location rates are up to as high as 95.570% and 72.656% respectively. The self-test scheme can perform at-speed test and has no degradation of the original circuit performance, and the test time is independent of adder length.