A low power low phase noise wide frequency range PLL

This paper presents a low-noise, low-power, wide output frequency range phase-locked loop (PLL) for WLAN/WiFi transceivers. By employing a dual-symmetric CMOS cross-coupled pair differential inductor voltage-controlled oscillator (VCO), the design achieves low phase noise. In addition, an improved phase frequency detector (PFD) and a programmable low-mismatch charge pump (CP) with feedback compensation bias control are used to mitigate bandwidth and noise variations caused by different reference frequencies. The improved charge pump PLL (CPPLL) is designed in 65 nm CMOS process, and the chip layout occupies an area of 0.28 mm2. Post-layout simulation results indicate that the PLL has a tuning range of 4.6 GHz to 6 GHz, a phase noise of 111.7 dBc/Hz at 1 MHz offset at 5 GHz, a total power consumption of 7.14 mW, and a lock time of about 9 mu s.