A 3D IC self-test and recovery method based on Through Silicon Via defect modeling

被引:0
|
作者
Yu, Le [1 ,2 ]
Yang, Hai-Gang [1 ]
Xie, Yuan-Lu [1 ]
Zhang, Jia [1 ,2 ]
Zhang, Chun-Hong [1 ,2 ]
Wei, Yuan-Feng [1 ]
机构
[1] Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China
[2] Graduate University, Chinese Academy of Sciences, Beijing 100049, China
关键词
Compilation and indexing terms; Copyright 2024 Elsevier Inc;
D O I
10.3724/SP.J.1146.2012.00048
中图分类号
学科分类号
摘要
Defects - Three dimensional computer graphics
引用
收藏
页码:2247 / 2253
相关论文
共 50 条
  • [31] Design of Novel Through Silicon via Structures for Reduced Crosstalk Effects in 3D IC Applicationse
    Ganimidi, Mounika
    Kumar, Vobulapuram Ramesh
    INTELLIGENT COMMUNICATION, CONTROL AND DEVICES, ICICCD 2017, 2018, 624 : 599 - 605
  • [32] Shielding Structures for Through Silicon Via (TSV) to Active Circuit Noise Coupling in 3D IC
    Lim, Jaemin
    Lee, Manho
    Jung, Daniel H.
    Kim, Jonghoon J.
    Choi, Sumin
    Lee, Hyunsuk
    Kim, Joungho
    2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, 2015, : 248 - 251
  • [33] Precise RLGC Modeling and Analysis of Through Glass Via (TGV) for 2.5D/3D IC
    Kim, Jihye
    Hwang, Insu
    Kim, Youngwoo
    Cho, Jonghyun
    Sundaram, Venky
    Tummala, Rao
    Kim, Joungho
    2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2015, : 254 - 259
  • [34] 3D TCAD Modeling For Stress Management In Through Silicon Via (TSV) Stacks
    Xu, Xiaopeng
    Karmarkar, Aditya
    STRESS MANAGEMENT FOR 3D ICS USING THROUGH SILICON VIAS: INTERNATIONAL WORKSHOP ON STRESS MANAGEMENT FOR 3D ICS USING THROUGH SILICON VIAS, 2011, 1378 : 53 - +
  • [35] Modeling and Electromagnetic Analysis of Multilayer Through Silicon Via Interconnect for 3D Integration
    Yan, Zhaowen
    Kang, Ting
    Zhang, Wei
    Wang, Jianwei
    INTERNATIONAL JOURNAL OF ANTENNAS AND PROPAGATION, 2015, 2015
  • [36] Through-Silicon Via Capacitance-Voltage Hysteresis Modeling for 2.5-D and 3-D IC
    Kim, Dong-Hyun
    Kim, Youngwoo
    Cho, Jonghyun
    Bae, Bumhee
    Park, Junyong
    Lee, Hyunsuk
    Lim, Jaemin
    Kim, Jonghoon J.
    Piersanti, Stefano
    de Paulis, Francesco
    Orlandi, Antonio
    Kim, Joungho
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2017, 7 (06): : 925 - 935
  • [37] A Built-In Self-Test Scheme for the Post-Bond Test of TSVs in 3D ICs
    Huang, Yu-Jen
    Li, Jin-Fu
    Chen, Ji-Jan
    Kwai, Ding-Ming
    Chou, Yung-Fa
    Wu, Cheng-Wen
    2011 IEEE 29TH VLSI TEST SYMPOSIUM (VTS), 2011, : 20 - 25
  • [38] Through Silicon Via (TSV) Noise Coupling Effects on RF LC-VCO in 3D IC
    Lim, Jaemin
    Cho, Jonghyun
    Lee, Manho
    Jung, Daniel H.
    Choi, Sumin
    Lee, Hyunsuk
    Kim, Joungho
    Kim, Hyungsoo
    Kim, Yongju
    Kim, Yunsaing
    2014 IEEE 23RD CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, 2014, : 53 - 56
  • [39] Analytical Model of the Coupling Capacitance between Cylindrical Through Silicon Via and Horizontal Interconnect in 3D IC
    Yu, Wenjian
    Yang, Siyu
    Zhang, Qingqing
    2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2013,
  • [40] Self-Test Methodology and Structures for Pre-Bond TSV Testing in 3D-IC System
    Wang, Chao
    Zhou, Jun
    Zhao, Bin
    Liu, Xin
    Royannez, Philippe
    Je, Minkyu
    2012 IEEE ASIAN SOLID STATE CIRCUITS CONFERENCE (A-SSCC), 2012, : 393 - 396