Omitting cache look-up for high-performance, low-power microprocessors

被引：0

作者：

Inoue, Koji ^{[1
]}

Moshnyaga, Vasily G. ^{[1
]}

Murakami, Kazuaki ^{[2
]}

机构：

[1] Department of Electonics and Computer Science, Fukuoka University, Japan

[2] Department of Informatics, Kyushu University, Japan

来源：

IEICE Transactions on Electronics | 2002年 / E85-C卷 / 02期

关键词：

Buffer storage - Computer architecture - Energy utilization;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called history-based tag-comparison (HBTC) cache. The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.

引用

页码：279 / 287

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