Forwarding unit generation for loop pipelining in high-level synthesis

被引：0
|
作者：
Kusakabe, Shingo [1 ]
Seto, Kenshu [1 ]
机构：
[1] Tokyo City University, Setagaya,Tokyo,158-8557, Japan
来源：
IPSJ Transactions on System LSI Design Methodology | 2014年 / 7卷
关键词：
Dependence - Dependence analysis - Forwarding - High speed circuit - Loop pipelining - Memory access - Source code transformation - State-of-the-art techniques;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：119 / 124
相关论文
共 50 条
  • [1] Loop Pipelining in High-Level Synthesis with CCC
    Dimitriou, Georgios
    Dossis, Michael
    Stamoulis, Georgios
    2017 6TH INTERNATIONAL CONFERENCE ON MODERN CIRCUITS AND SYSTEMS TECHNOLOGIES (MOCAST), 2017,
  • [2] Toward Speculative Loop Pipelining for High-Level Synthesis
    Derrien, Steven
    Marty, Thibaut
    Rokicki, Simon
    Yuki, Tomofumi
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 39 (11) : 4229 - 4239
  • [3] Enabling Adaptive Loop Pipelining in High-Level Synthesis
    Dai, Steve
    Liu, Gai
    Zhao, Ritchie
    Zhang, Zhiru
    2017 FIFTY-FIRST ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS, AND COMPUTERS, 2017, : 131 - 135
  • [4] Loop Splitting for Efficient Pipelining in High-Level Synthesis
    Liu, Junyi
    Wickerson, John
    Constantinides, George A.
    2016 IEEE 24TH ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM), 2016, : 72 - 79
  • [5] Flushing-Enabled Loop Pipelining for High-Level Synthesis
    Dai, Steve
    Tan, Mingxing
    Hao, Kecheng
    Zhang, Zhiru
    2014 51ST ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2014,
  • [6] Runtime Dependency Analysis for Loop Pipelining in High-Level Synthesis
    Alle, Mythri
    Morvan, Antoine
    Derrien, Steven
    2013 50TH ACM / EDAC / IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2013,
  • [7] Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis
    Liu, Junyi
    Wickerson, John
    Bayliss, Samuel
    Constantinides, George A.
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 37 (09) : 1802 - 1815
  • [8] Minimal-Area Loop Pipelining for High-Level Synthesis with CCC
    Dimitriou, Georgios
    Dossis, Michael
    Stamoulis, Georgios
    2017 SOUTH EASTERN EUROPEAN DESIGN AUTOMATION, COMPUTER ENGINEERING, COMPUTER NETWORKS AND SOCIAL MEDIA CONFERENCE (SEEDA-CECNSM), 2017, : 13 - 20
  • [9] Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis
    Fiege, Nicolai
    Sittel, Patrick
    Zipf, Peter
    2022 32ND INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, FPL, 2022, : 262 - 269
  • [10] Scaling Up Loop Pipelining For High-Level Synthesis: A Non-Iterative Approach
    Rosa, Leandro de Souza
    Bonato, Vanderlei
    Bouganis, Christos-Savvas
    2018 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT 2018), 2018, : 65 - 72
12345