共 50 条
- [32] Single Bit Hybrid Full Adder Cell by Gate Diffusion Input and Pass Transistor Logic Technique PROCEEDINGS OF 2017 IEEE INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRICAL TECHNOLOGY FOR GREEN ENERGY (ICAETGT), 2017, : 37 - 42
- [34] Low-power circuit implementation for partial-product addition using pass-transistor logic IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 1999, 146 (03): : 124 - 129
- [35] Design Of Low Voltage Flip-flop Based On Complementary Pass-Transistor Adiabatic Logic Circuit 2016 WORLD CONFERENCE ON FUTURISTIC TRENDS IN RESEARCH AND INNOVATION FOR SOCIAL WELFARE (STARTUP CONCLAVE), 2016,
- [36] A novel low power energy recovery full adder cell NINTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS, 1999, : 380 - 383
- [37] CNFET-based designs of Ternary Half-Adder using a novel "decoder-less" ternary multiplexer based on unary operators MICROELECTRONICS JOURNAL, 2020, 96
- [39] Design of a low power 7-bit serial counter with Energy Economized Pass-transistor Logic (EEPL) ICECS 96 - PROCEEDINGS OF THE THIRD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS, VOLS 1 AND 2, 1996, : 1033 - 1036
- [40] A novel hybrid pass logic with static CMOS output drive full-adder cell PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V: BIO-MEDICAL CIRCUITS & SYSTEMS, VLSI SYSTEMS & APPLICATIONS, NEURAL NETWORKS & SYSTEMS, 2003, : 317 - 320